Significance of IPUx_CH_BUFx_RDYx register in IPU

[pradeepas]

Hello,

I'm developing an IPU driver for a custom application. I am half way into the configurations. I am using the SDK as a reference.

In the SDK under the function "ipu_capture_setup" there is a place where we toggle the IPUx_CH_BUFx_RDYx register bits.

ipu_channel_buf_ready(ipu_index, csi_in_channel, 0);

ipu_channel_buf_ready(ipu_index, csi_in_channel, 1);

I would like to know why we are doing this? Also, in this case if we are using double buffering do we need to do the same for IPUx_CH_BUF0_RDY0 and IPUx_CH_BUF1_RDY0 registers? (channel I am using is 0)

Thank you.

[Yuri]

  Basically : "the IPU refreshes the screen every VSYNC event. IPU reads a buffer from the DDR.
And switch to a new buffer upon a trigger (buffer ready). IPU will switch to the next buffer only
when they completes updating the screen with the current buffer."

Have a great day,
Yuri

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[pradeepas]

So if I am not using the IPU display feature, I do not need to set or clear IPUx_CH_BUFx_RDYx registers. Am I correct?

[Yuri]

When using IPU for capture, frame-by-frame approach is used too, this means - strictly speaking -

it is needed to check buffer ready registers, if ARM core is involved in double buffering (software polling).

Regards,

Yuri.

[pradeepas]

In IPU capture context, does buffer ready means "buffer is ready to capture data" or "buffer has finished capturing data" ?

[Yuri]

Hello,

ARM core finished operation, so buffer is ready to capture.

Regards,

Yuri.