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Seperate MDIO for dual phys on imx6sx

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Seperate MDIO for dual phys on imx6sx

‎12-01-2020 02:19 PM
1,276件の閲覧回数
brycejohnson
Contributor I

Hi,

I have two phys on a custom board with a imx6sx using seperate MDIO to communicate with the phys, a ksz9031 and ksz8051. Both phys have address of 1.  Do they need a different address if it is on a different MDIO bus?

I can get fec2 to work (ksz8051) by removing fec1 from the dts.  If I have both in there then only fec1 works(kfz9031)

Here is the relevant information in the dts.

Any advice or things to try? 

Thanks

Bryce

&fec1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_reset>;
		phy-mode = "rgmii";
        phy-handle = <&ethphy0>;
        phy-reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; 
		fsl,magic-packet;
        status = "okay";
        mdio {
                #address-cells = <1>;
                #size-cells = <0>;
                ethphy0: ethernet-phy@1 {
                    compatible = "ethernet-phy-ieee802.3-c22";
                    reg = <1>;
                };
        };
};

&fec2 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_reset>;
		phy-mode = "rmii";
        phy-handle = <&ethphy1>;
        phy-reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;		
	    phy-reset-duration = <100>;
        phy-reset-post-delay = <1000>;		
		fsl,magic-packet;
        status = "okay";
        mdio {
                #address-cells = <1>;
                #size-cells = <0>;
                ethphy1: ethernet-phy@1 {
   					compatible = "ethernet-phy-ieee802.3-c22";
                    reg = <1>;
					max-speed = <100>;
                };
        };
};

	



enet1 {
		pinctrl_enet1: enet1grp {
			fsl,pins = <
				MX6SX_PAD_ENET1_MDIO__ENET1_MDIO	0x1b0b0
				MX6SX_PAD_ENET1_MDC__ENET1_MDC		0x1b0b0
				MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0	0x30b1
				MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1	0x30b1
				MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2	0x30b1
				MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3	0x30b1
				MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC	0x30b1
				MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN	0x30b1
				MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0	0x3081
				MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1	0x3081
				MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2	0x3081
				MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3	0x3081
				MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK		0x30b1
				MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN	0x3081
				MX6SX_PAD_ENET1_TX_CLK__ENET1_TX_CLK	0xb0b0
				MX6SX_PAD_RGMII2_TD3__GPIO5_IO_21  		0x30b1
			>;
		};
		pinctrl_enet1_reset: enet1resetgrp {
			fsl,pins = <
				MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 		0xb0b0
			>;
		};
	};

	enet2 {
		pinctrl_enet2: enet2grp {
			fsl,pins = <
				MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0	0x30b1
				MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1	0x30b1
				MX6SX_PAD_RGMII2_TD2__GPIO5_IO_20  		0x30b1
				MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN	0x30b1
				MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0	0x3081
				MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1	0x3081
				MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK	0x3081
				MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN	0x3081
				MX6SX_PAD_ENET1_COL__ENET2_MDC			0x30b1
				MX6SX_PAD_ENET1_CRS__ENET2_MDIO			0x30b1				
				MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x3081
			>;
		};
		pinctrl_enet2_reset: enet2resetgrp {
			fsl,pins = <
				MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 0xb0b0
			>;
		};
	};

 

 

 

 

 

 

 

 

 

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‎12-04-2020 02:15 PM
1,236件の閲覧回数
brycejohnson
Contributor I

I am still unable to get this to work. I also got in touch with a vendor that contacted an NXP FAE, but wanted keep this up to date as well here.

 

I modified one phy to use mido address 3.  They are still on two seperate mdio sets of pins. 

 

I tried this:

&fec1 {

        pinctrl-names = "default";

        pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_reset>;

           phy-mode = "rgmii";

        phy-handle = <&ethphy0>;

        phy-reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;

           fsl,magic-packet;

        status = "okay";

        mdio {

                #address-cells = <1>;

                #size-cells = <0>;

                ethphy0: ethernet-phy@3 {

                    compatible = "ethernet-phy-ieee802.3-c22";

                    reg = <3>;

                };

                ethphy1: ethernet-phy@1 {

                           compatible = "ethernet-phy-ieee802.3-c22";

                    reg = <1>;

                           max-speed = <100>;

                };                  

          

        };

};

&fec2 {

        pinctrl-names = "default";

        pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_reset>;

           phy-mode = "rmii";

        phy-handle = <&ethphy1>;

        phy-reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;      

         phy-reset-duration = <100>;

        phy-reset-post-delay = <1000>;     

           fsl,magic-packet;

        status = "okay";

};

 

and this:

 

&fec1 {

        pinctrl-names = "default";

        pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_reset>;

           phy-mode = "rgmii";

        phy-handle = <&ethphy0>;

        phy-reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;

           fsl,magic-packet;

        status = "okay";

        mdio {

                #address-cells = <1>;

                #size-cells = <0>;

                ethphy0: ethernet-phy@3 {

                    compatible = "ethernet-phy-ieee802.3-c22";

                    reg = <3>;

                };

                ethphy1: ethernet-phy@1 {

                           compatible = "ethernet-phy-ieee802.3-c22";

                    reg = <1>;

                           max-speed = <100>;

                };                   

          

        };

};

&fec2 {

        pinctrl-names = "default";

        pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_reset>;

           phy-mode = "rmii";

        phy-handle = <&ethphy1>;

        phy-reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;      

         phy-reset-duration = <100>;

        phy-reset-post-delay = <1000>;     

           fsl,magic-packet;

        status = "okay";

        mdio {

                #address-cells = <1>;

                #size-cells = <0>;

                ethphy1: ethernet-phy@1 {

                           compatible = "ethernet-phy-ieee802.3-c22";

                    reg = <1>;

                           max-speed = <100>;

                };                  

          

        };

};

 

If I remove fec1 (and move the mdio under fec2) then I fec2 will work.  Otherwise only fec1 is working.

 

Thanks

Bryce

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‎12-01-2020 07:52 PM
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weidong_sun
NXP TechSupport
NXP TechSupport

Hi,

In your device tree, there are 2 mdio nodes defined, which will cause conflicts. You need to define it like this:

&fec1 {
      pinctrl-names = "default";
      pinctrl-0 = <&pinctrl_enet1>;
      phy-supply = <&reg_enet_3v3>;
      phy-mode = "rgmii-id";
      phy-handle = <&ethphy1>;
      phy-reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
      status = "okay";

      mdio {
               #address-cells = <1>;
               #size-cells = <0>;

               ethphy1: ethernet-phy@1 {
               reg = <1>;
             /* at803x,eee-disabled;*/
     };

            ethphy2: ethernet-phy@2 {
                          reg = <2>;
              /*           at803x,eee-disabled;*/
          };
   };
};

&fec2 {
            pinctrl-names = "default";
            pinctrl-0 = <&pinctrl_enet2>;
            phy-mode = "rgmii-id";
            phy-handle = <&ethphy2>;
            status = "okay";
};

See imx6sx-sdb.dtsi, please!

 

Hope this information is helpful to you.

Have a nice day!

B.R,

weidong

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‎12-01-2020 08:36 PM
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brycejohnson
Contributor I

Hi weidong,

Thanks for the response.

On the imx6sx-sdb.dtsi the mdio bus is shared between on the two phys on the same mdio bus, correct?.  I don't have the two phys on the same mdio bus, I am using one phy on different mdio pins.

mdio pinctrl for fec1:

				MX6SX_PAD_ENET1_MDIO__ENET1_MDIO	0x1b0b0
				MX6SX_PAD_ENET1_MDC__ENET1_MDC		0x1b0b0

 

mdio pinctrl for fec2

				MX6SX_PAD_ENET1_COL__ENET2_MDC			0x30b1
				MX6SX_PAD_ENET1_CRS__ENET2_MDIO			0x30b1

 

 Even though I am using two different MDIO sets of pins, I need to declare it in fec1 and have a different mdio address (and do a board mod to have different strapping resistors)?  So bascially mdio is shared even though it has two sets of pins?

 

Thanks

Bryce

 

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‎05-10-2024 03:28 AM
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smanni
Contributor II

Hi brycejohnson,

by default FECs share the same MDIO bus (see FEC_QUIRK_SINGLE_MDIO). This is often used in design to save pins but it is not your case because you want to use two different MDIO buses.

To fix the problem just set the property fsl,mii-exclusive for both fec1 and fec2 in dts and both PHYs will work.

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