SD2 ports can't be used as GPIO on imx8mq?

[thomasnam]

Hi

I'm working with imx8mq-evk board and custom board.

I have tried to assign SD2_WP, SD2_DATA2, SD2_DATA3 port to GPIO output and test it. But they are not controlled.

So please advise me.

I have set the PINMUX as below in dts file.

MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20			0x49
MX8MQ_IOMUXC_SD2_DATA2_GPIO2_IO17		0x4f
MX8MQ_IOMUXC_SD2_DATA3_GPIO2_IO18		0x49

After boot, the port status is as below.

[root:~] /unit_tests/memtool IOMUXC.SW_MUX_CTL_PAD_SD2_WP
SOC: i.MX8MQ
IOMUXC   Addr:0x30330000 
  IOMUXC.SW_MUX_CTL_PAD_SD2_WP Addr:0x303300F0 Value:0x00000005 - SW_MUX_CTL Register
     IOMUXC.SW_MUX_CTL_PAD_SD2_WP.MUX_MODE(0..2)        :0x5
             Select 1 of 2 iomux modes to be used for pad: SD2_WP
     IOMUXC.SW_MUX_CTL_PAD_SD2_WP.SION(4..4)    :0x0
             Force the select mux mode Input path no matter of MUX_MODE functionality

[root:~]/unit_tests/memtool IOMUXC.SW_PAD_CTL_PAD_SD2_WP
SOC: i.MX8MQ
IOMUXC   Addr:0x30330000 
  IOMUXC.SW_PAD_CTL_PAD_SD2_WP Addr:0x30330358 Value:0x00000016 - SW_PAD_CTL Register
     IOMUXC.SW_PAD_CTL_PAD_SD2_WP.DSE(0..2)     :0x6
             Select one out of next values for pad: SD2_WP
     IOMUXC.SW_PAD_CTL_PAD_SD2_WP.SRE(3..4)     :0x2
             2-bit slew rate control signals to select between 50,100 and 200MHz I/O cell operation frequency range with reduced switching noise.
     IOMUXC.SW_PAD_CTL_PAD_SD2_WP.ODE(5..5)     :0x0
             Select one out of next values for pad: SD2_WP
     IOMUXC.SW_PAD_CTL_PAD_SD2_WP.PUE(6..6)     :0x0
             Control signal to select internal pullup resistor
     IOMUXC.SW_PAD_CTL_PAD_SD2_WP.HYS(7..7)     :0x0
             Control signal to select Schymitt trigger
     IOMUXC.SW_PAD_CTL_PAD_SD2_WP.LVTTL(8..8)   :0x0
             Control signal to select LVTTL input

But the GPIO pull up configuration is different with DTS value and GPIO output can't be controlled.

So I have wrote the configuration for pull-up-enable .

[root:~]/unit_tests/memtool IOMUXC.SW_PAD_CTL_PAD_SD2_WP=0x49
SOC: i.MX8MQ
write 0x00000049 to 0x30330358
[root:~]/unit_tests/memtool IOMUXC.SW_PAD_CTL_PAD_SD2_WP
SOC: i.MX8MQ
IOMUXC   Addr:0x30330000 
  IOMUXC.SW_PAD_CTL_PAD_SD2_WP Addr:0x30330358 Value:0x00000049 - SW_PAD_CTL Register
     IOMUXC.SW_PAD_CTL_PAD_SD2_WP.DSE(0..2)     :0x1
             Select one out of next values for pad: SD2_WP
     IOMUXC.SW_PAD_CTL_PAD_SD2_WP.SRE(3..4)     :0x1
             2-bit slew rate control signals to select between 50,100 and 200MHz I/O cell operation frequency range with reduced switching noise.
     IOMUXC.SW_PAD_CTL_PAD_SD2_WP.ODE(5..5)     :0x0
             Select one out of next values for pad: SD2_WP
     IOMUXC.SW_PAD_CTL_PAD_SD2_WP.PUE(6..6)     :0x1
             Control signal to select internal pullup resistor
     IOMUXC.SW_PAD_CTL_PAD_SD2_WP.HYS(7..7)     :0x0
             Control signal to select Schymitt trigger
     IOMUXC.SW_PAD_CTL_PAD_SD2_WP.LVTTL(8..8)   :0x0
             Control signal to select LVTTL input

The PUE is changed but the GPIO output control is not working.

The ports are not connected anywhere just opened.

How can I use SD2 ports as GPIO?

 Best regards,

[igorpadykov]

Hi DaeHyun

one can look at i.MX8MQ gpio tutorial

http://variwiki.com/index.php?title=DART-MX8M_GPIO

for "GPIO output control is not working" additionally one can check settings of

GPIO direction register (GPIOx_GDIR).

Best regards
igor

[thomasnam]

Hi Igor,

Thanks for your guide.

I have checked the direction but it is correct and the GPIO output is still not working.

[root:/sys/class/gpio] /unit_tests//memtool GPIO2.GDIR
SOC: i.MX8MQ
GPIO2    Addr:0x30210000 
  GPIO2.GDIR Addr:0x30210004 Value:0x001E0400 - GPIO_GDIR functions as direction control when the IOMUXC is in GPIO mode.
     GPIO2.GDIR.GDIR(0..31)     :0x1e0400
             GPIO direction bits.

[root:/sys/class/gpio]cat /sys/kernel/debug/gpio
gpiochip0: GPIOs 0-31, parent: platform/30200000.gpio, 30200000.gpio:
 gpio-13  (                    |vdd_arm             ) out lo 

gpiochip1: GPIOs 32-63, parent: platform/30210000.gpio, 30210000.gpio:
 gpio-49  (                    |sysfs               ) out hi 
 gpio-50  (                    |sysfs               ) out hi 
 gpio-52  (                    |sysfs               ) out hi 

gpiochip2: GPIOs 64-95, parent: platform/30220000.gpio, 30220000.gpio:

gpiochip3: GPIOs 96-127, parent: platform/30230000.gpio, 30230000.gpio:

gpiochip4: GPIOs 128-159, parent: platform/30240000.gpio, 30240000.gpio:

 In this status, the GPIO outs are low.

Are there any other checkpoints?

[thomasnam · Accepted solution]

When I connect the external pull register the GPIO output looks working but it is not normal.

I think the pin assign should move to other pins.