Running DDR3L below its specified frequency with iMX6UL

[pooperfish]

It looks like the iMX6UL has been validated with DDR3-1600 (800MHz clock). Given the processor runs slower than this, is it correct to assume the processor has no issues clocking the memory below its specified bus frequency? Would there be any issues interfacing the i.MX6UL to DDR3-1866?

Thanks. 

[pooperfish]

The EVK (part number MCIMX6UL-EVKB) has DDR3-1600 fitted!

[art]

So, DDR3 opertaes below its upper grade.

[art]

No, i.MX6UL has never been validated for 800MHz DDR clock frequency (DDR3-1600 grade). Its maximum specified DDR clock frequency is 400MHz, meaning DDR3-800 speed grade, please refer to the part's Data Sheet document, available on the processor's Documentation web page:

http://www.nxp.com/products/microcontrollers-and-processors/arm-processors/i.mx-applications-process...

Have a great day,
Artur

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[bernhardfink]

This seems to be a misinterpretation on your side

The data sheet for the i.MX6 UL specifies the following DDR devices:

16-bit LP-DDR2-800, 16-bit DDR3-800 and LV-DDR3-800

Also the Reference Manual for the 6UL specifies the DDR for 400MHz:

MMDC running at up to 400 MHz (800 MT/s), see CCM block for actual clock frequencies supported.

Regards,

Bernhard.

[pooperfish]

Thanks for your response Bernhard.

The datasheet does mention LV-DDR3-800 and the RM states a max MMDC clock of 396MHz. Nevertheless, the iMX.6UL EVK has a Micron MT41K256M16HA-125:E fitted, which is a DDR3-1600 device.

Clearly the "faster" DDR3L is compatible with the "slower" MMDC, and I was wondering how this is achieved and whether there might be any issues, since I'm looking at interfacing to DDR3-1866.

I've looked more closely at the Micron DDR3L specifications, and it seems the speed grade (CL) is configurable, allowing tCK to be increased beyond the specified 1.07ns. This sounds like the answer, although I will dig a bit more. 

Has anyone had any experience with this?

Cheers,

Nick