Repeated eth interface "Link is up/Link is down", PHY clock issues

Showing results for 
Search instead for 
Did you mean: 

Repeated eth interface "Link is up/Link is down", PHY clock issues

Contributor II

processor: i.MX7Dual

kernel: rel_4.1.15_2.1.0_ga

We've come across an issue related to the PHY driver, where upon boot the interface repeatedly reports "Link is up/Link is down". The probability of this symptom appearing differs from board to board, and it seems to be related to the clk to the phy being disabled at some point during the driver probe. Monitoring related signals showed clk was on before reset was pusled, clk is then disabled for ~4 seconds. To temporarily remedy this issue, we commented out line 3612 in fec_main.c:


   fec_enet_clk_enable(ndev, false);   

This seemed a bit brutish, so after some investigation I found there seems to be some history of forum questions and various unmerged patches that claim to fix this issue (one of them identical to our quick resolution). See: 
   Problem with "swinging" ethernet link on i.MX28 based device - Patchwork - patchset untested by us as of yet.
   Google Groups - Similar patchset to above, seems to be further along though.

      Blames regression on commit e8fcfcd5684a4165fe3f86dd24baa14f1e3fad7e - same fix as we've done, mentioned above, seems to work. - report of same symptoms.

Any suggestions on the correct path forward? Any official patches related to this issue?



Labels (2)
Tags (1)
1 Reply

NXP TechSupport
NXP TechSupport

Hi Brandon

correct way is to avoid disabling enet clock, as processor may behave

inpredicatbly. If disabling, try to reinitialize ENET module anew.

Best regards
Note: If this post answers your question, please click the Correct Answer button. Thank you!

0 Kudos