Question, i.MX6UltraLight ERR010690

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Question, i.MX6UltraLight ERR010690

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SLICE
Contributor IV

Dear team,

I would like to ask about ERR010690, SNVS_LP registers reset issue, of i.MX6UL.

My customer is using i.MX6UL Rev.1.1 chips.

And they have a concern on ERR010690.

They have questions on ERR010690 as below.

Please give your answers to the following questions.

(1)

The power supply circuitry of their board is similar as your EVK board.

Can this issue mentioned in ERR010690 occur also on your EVK?

(2)

The customer is using SRTC backup by coin-cell.

In the description of ERR010690, the registers of SNVS_LP is not specified.

It is mentioned only as ‘SNVS_LP registers’.

Could you give the details about exactly what registers can be affected by this issue?

They want to know whether it is possible to affect their SRTC backup feature.

Thanks,

Miyamoto

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842 次查看
Yuri
NXP Employee
NXP Employee

Hello,

1.

  On the EVK scheme :

VDD_ARM_SOC_IN is controlled by DCDC_3V3_PG (3.3V is good),

but VDD_HIGH_IN is connected directly to DCDC_3V3. This means :

VDD_SOC_IN is ramping up when VDD_HIGH_IN is not higher than 3.0 V.

VDD_SOC_IN is ramping down when VDD_HIGH_IN is lower than 3.0 V.

VDD_SOC_IN is not ramping down earlier than VDD_HIGH_IN.

 

  So, the EVK should not be affected with the erratum. But the Errata recommends the following :

The workarounds below should be both used to avoid SNVS_LP registers reset issue:

• VDD_HIGH_IN power down is earlier than VDD_SOC_IN.

• VDD_HIGH_IN voltage power is less than or equal to 3.0 V.

 

The second item is not satisfied on the EVK.

 

 

2.

  All registers inside SNVS_LP may be reset. Please look at section 46.7.1 (SNVS Memory Map) of i.MX 6UltraLite Applications Processor Reference Manual, Rev. 1, 04/2016.

 

Have a great day,
Yuri

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843 次查看
Yuri
NXP Employee
NXP Employee

Hello,

1.

  On the EVK scheme :

VDD_ARM_SOC_IN is controlled by DCDC_3V3_PG (3.3V is good),

but VDD_HIGH_IN is connected directly to DCDC_3V3. This means :

VDD_SOC_IN is ramping up when VDD_HIGH_IN is not higher than 3.0 V.

VDD_SOC_IN is ramping down when VDD_HIGH_IN is lower than 3.0 V.

VDD_SOC_IN is not ramping down earlier than VDD_HIGH_IN.

 

  So, the EVK should not be affected with the erratum. But the Errata recommends the following :

The workarounds below should be both used to avoid SNVS_LP registers reset issue:

• VDD_HIGH_IN power down is earlier than VDD_SOC_IN.

• VDD_HIGH_IN voltage power is less than or equal to 3.0 V.

 

The second item is not satisfied on the EVK.

 

 

2.

  All registers inside SNVS_LP may be reset. Please look at section 46.7.1 (SNVS Memory Map) of i.MX 6UltraLite Applications Processor Reference Manual, Rev. 1, 04/2016.

 

Have a great day,
Yuri

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

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SLICE
Contributor IV

Hello Yuri

Thanks!

That is;

1.

This issue can be occur even on EVK.

2.

RTC also can be lost if the issue occur.

Right?

Best Regards,

Miyamoto

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Yuri
NXP Employee
NXP Employee

Hello,

  yes, You are right.  

Regards,

Yuri.

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