Question, DDR stress test i.MX6Q

[Aemj]

Dear team,

I would like to ask about DDR stress test.

My customer is facing the issue that the error occurs on DDR stress test(V.2.52) for their i.MX6Q proto-board.

They are using MCIMX6Q6AVT10AD for their proto-board and DDR3 is used for that.

For their board, MT41K512M16HA-107 x 4 are used.

And they are using ddr_stress_tester_jtag_v2.52.

As for ‘Write level HW calibration’, it can be completed normally.

And for ‘Starting DQS gating calibration’, they saw the following error message and it cannot be completed.

“ERROR FOUND, we can't get suitable value !!!! dram test fails for all values.”

They already saw the whole of DDR stress test can finish successfully on i.MX6Q-SDB, and they use the modified DS file for DDR stress test for their proto-board because the DDR3 chips used for their board are changed from DDR used for SDB.

The attached file, TEST.DS, is the ds file for their board.

The main change of the file from the one for SDB is the ‘row addresses’.

Do you have any ideas for the cause of this error?

Please let me know whether any changes of settings should be needed for DDR stress test for their proto-board other than ‘row address’ setting.

Thanks,

Miyamoto

Original Attachment has been moved to: TEST.DS.zip

[Yuri]

Hello,

please try to check the design, using section 1.1 (Schematic and Layout Design Rules) of the DDR3

Porting Guide

Freescale i.MX6 DRAM Port Application Guide-DDR3

  In particular, there is an Excel page named “MX6 DRAM Bus Length Check” in “HW Design Checking List

for i.Mx6”. Designer can use it for layout self-checking. Input trace length of the design into cells in pink circle then,

the bottom cell in same column may change  to red color if layout breaks the rule.

Recent design checklist may be found at

HW Design Checking List for i.MX6DQSDL

Have a great day,
Yuri

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