Hello NXP Team We have a situation in our project that we don’t know how to solve. It is related to the setting for the FlexSPI clock frequency. We have set it in the configuration tool (Tresos MCAL) to 133MHz. We have the following NAND chip connected: Micron-MT35XU02GCBA2G12-0AAT-datasheet.pdf As you can see, it supports max 166MHz for SDR communication and 200MHz for DDR communication. Because this chip boots in SDR mode, the first commands that we send are in SDR mode and these commands are write enable and switching to DDR mode. The problem that we are seeing is that the SCLK line has a frequency of approximately 266 MHz for those 2 SDR commands in the beginning, then it is 133MHz once we switch to DDR mode. So we are exceeding the specification of the connected chip for the SDR mode. We also want to keep at least 133MHz for DDR mode. We found no way to set separate frequencies for SDR and DDR mode in the configuration tool. In the iMX8 reference manual (e.g. Chapter 18.2.4.4) I can only find that the clock in SDR mode is equal to the input clock, and the clock in DDR mode is half of the input clock. Do you have any suggestions on how we can do separate configurations for the clock, so that we don’t exceed the maximum clock in SDR mode, but to also be able to set a high clock for DDR mode? Also can you explain why the SDR clock is double than what we expect, and the DDR is actually at the set value? (i.e. Why is it not actually 133MHz for SDR and 66MHz for DDR?)
