Placing a delay in SPI communications i.MX7d

[suzi_orourke]

Looking for ways to modify the timing for a chip select line when using ecspi on an imx7d. We are using a device that becomes 'ready' to receive a message, only after a set time period has passed after the chip select line goes low. This doesn't seem doable with the standard device tree, or ecspi driver. We have measured the time between the chip select going low, and the clock starting to be 120 nanoseconds, and that is the measurement we need to increase. 

There are several ways we have considered attempting to do this. 
1) Change the device tree to mux the cs pins as gpio pins and remove the DMA control from the SPI bus to allow free movement of the gpio pins separate from the spi communication. There are down sides to this, as it will slow down the transactions and require more cpu cycles to process each transaction. 

2) Modify the register that controls timing (ECSPIx_PERIODREG ?). This leads to a few questions, such as: Can this be done in the program that will be running on our board, or does this need to be done in the driver? I found a reference to the timing in this question regarding ECSPIx_PERIODREG Can ECSPI PERIODREG be modified any time? It seems that this should be done in the driver, or somewhere that it will be read during initialization which suggests not to look for a way to do this in our program. Looking at the IMX7DRM pdf for the i.MX 7Dual, the ECSPIx_PERIODREG seems like we could set it to 0x8000 to 0x1F8000 to change the delay between the chip select and the clock's first cycle. 

Is there another way? 

Please let me know if there is any information that is missing that would be helpful. 

[Yuri]

@suzi_orourke 

Hello,

   I think, that only the first approach (to use GPIO as CS) can solve
the issue. Generally ECSPIx_PERIODREG is used to insert pause between consecutive
SPI transfers.

Regards,
Yuri.

[suzi_orourke]

Thank you Yuri for your reply. I'm a little confused, because this is one of the lines from the manual: 
ECSPI_PERIODREG also contains the CSD CTRL field used to insert a delay between the Chip Select's active edge and the first SPI Clock edge. 

and further:
Chip Select Delay Control bits. This field defines how many SPI clocks will be inserted between the chip select's active edge and the first SPI clock edge.

Rereading this, it seems it will insert a delay where I want it, right between the CS active edge and the first clock edge. This to me says  Did I misunderstand it? 

If I were to try to add a delay here, through this, how do I access this register? Is it in one of the header files for the ecspi driver? 

The GPIO as CS approach I have been told has the drawbacks I listed, is this accurate in your understanding? Is removing the DMA necessary for this? 

[rtljopl]

For anybody else looking for this issue. Here is a patch that allows you to set this field from device tree configuration.

[Yuri]

@suzi_orourke 

Hello,

  Correct, it is possible to use bit field CSD_CTL (Chip Select Delay Control).
You may try to use driver probe function spi_imx_probe(), which performs initialization
and registration of the SPI  device-specific structure with SPI core driver. The driver probes
for memory and IRQ resources. Configures the IOMUX to enable ECSPI I/O pins, requests for IRQ
and resets the hardware.

https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/spi/spi-imx.c

https://www.nxp.com/docs/en/reference-manual/IMX_REFERENCE_MANUAL.pdf

Regards,
Yuri.