I'm developing an application where I use the ECSPI peripheral to trigger an external ADC to perform a conversion and simultaneously read back the previous conversion. The sample rate is a (slow) 100Hz and I generate this timing by using a slow SPI clock and a large value in the ECSPI PERIODREG. I have the ECSPI configured to begin transfers as soon as the TXFIFO has data and to continue transferring until it is empty. By keeping the TXFIFO stuffed with NOP commands for the ADC, I ensure a steady flow of samples at the intended rate.
A complication arises in that I'm trying to keep the sample rate on this input channel roughly synchronized to another 100Hz input channel sending data over the CANbus. The channels can wander relative to each other since they are not driven from the same clock source.
My intended solution (since I have no control over the CANbus input) is to tweak the sample rate of my ADC up or down a little, based on relative input queue depths, to try to keep them even. I do this by writing slightly smaller or larger (respectively) values into PERIODREG based on the current relative queue depths. The ADC then runs at either (about) 99Hz, 100Hz, or 101Hz at various times - with the long-term average frequency matching the actual frequency of the CANbus data channel.
My problem is that when I just do this without regard for what the ECSPI peripheral is doing at the time I write the PERIODREG I seem to cause occasional interruptions in the SPI transfers to the ADC. I've tried clearing TC in the STATREG and then waiting for it to be set again before writing PERIODREG, but that didn't make a difference. Is there a different approach I can use to find a safe time to update PERIODREG or is this approach just not going to work?
Alternative suggestions are very welcome. Thanks!