Pin assignment of imx8QXP connecting two DDR3Ls.

[yoshihiro_takah]

Hello,
 
I design circuit boad including I.MX8QXP and two DDR3Ls.
And I have a question about pin assignment of I.MX8QXP.
 
I.MX8QXP: MIMX8QX6AVLFZAC
DDR3L: 256M x 16 (M41K256M16TW)
 
Q.1
Which pin assignment is correct using I.MX8QXP and two DDR3Ls?
 
Assigmnet A:
<From DQ0 to DQ15>
ODT0  AB6
CK0P W5
CK0N Y6
CKE0 N7
CS0 K6
 
<From DQ16 to 31>
ODT1  K8
CK1P P6
CK1N N5
CKE1 L5
CS1 K2

Assigmnet B:
<Common connection : From DQ0 to DQ15 and  from DQ16 to DQ31>
ODT  AB6
CKP W5
CKN Y6
CKE N7
CS K6
ODT1  K8 （NC）
CK1P P6 （NC）
CK1N N5 （NC）
CKE1 L5 （NC）
CS1 K2  （NC） 
  
Q2.
I want to know about data swapping of i.MX8QXP.
　
Is there any problem if the pins are replaced on the i.MX8QXP side and DDR3L side within each byte?
 

Thanks
Takahashi

[art · Accepted solution]

Hello,

1. The correct DDR3L interface signal interconnection table is as shown below.

i.MX8QXP     1st DDR3L chip

DQ[15:0]        DQ[15:0]
ODT0 AB6     ODT
CK0P W5       CK_P
CK0N Y6        CK_N
CKE0 N7        CKE
CS0 K6           CS

i.MX8QXP       2nd DDR3L chip

DQ[31:16]       DQ[15:0]
ODT0 AB6      ODT
CK0P W5        CK_P
CK0N Y6         CK_N
CKE0 N7         CKE
CS0 K6            CS

I.e. the same clock/clock enable/chip select/ODT signals should be used for both DDR3L chips. Is it what you mean as your Assignment B? If so, it is correct.

2. It's OK to swap data bits within the same byte lane (but not across the byte lanes).

Best Regards,
Artur