Could some explain this please.. .I'm looking at DTS for my NXP SoC and a COM/board, trying to locate some peripherals and checking addresses.
What I cannot understand is what I see in DTS/Linux addresses vs what they are in SoC User guide, i.e. physical devices per NXP guide.
So e.g.:
What I thought / expected to see is something like , for serial 0 as UART1 address i.e :
As for example in device tree here :
This is from this link :https://www.emcraft.com/som/imx-8m/using-imx-8m-uart-ports-in-linux
In the above tree I can directly map that UART3 address to the address in the UG, i.e
So.. why do I have my serials starting at 0x5a......... ?
I have similar issue understanding what Linux's shows me for my GPIO ports:
Again, not addresses per my UG... Where does this come from, how to map to physical addresses to get actual physical peripheral ..?
If this is some standard device tree method to remap these, could you provide a link explaining how this works..?
I'm still lost on it, if you don't mind sending NXP's link to the document / User Guide you referring to?
The first image is from the actual running system. Yes, it traces as having LPUART.
But the chip you have referred to i.MX8QM, if I check overview at NXP's site: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-proces...
This has only one 4 core A53 complex, but my booted chip has 6 cores total managed by Linux, so I cannot find one QM variant with 6 cores - presumably A53 + A72 .. ?
Which iMX8 M then has 6 cores ?
@AldoG Thank you, now its starting to look much better.
Is there similar one for the GPIO ones ..? I think I'm looking into Low Speed I/O sub-system but I cannot find a similar memory map for that sub-section for my I/O ...
.. and answering my own question ...
Ta daaam
Thank you things starting to look more sensible now!
