Hi,
The lead time of the PCA9450A and the PCA9450AA is 52 weeks. From the technical point of view, what is needed that the i.MX8M Mini with LPDDR4 is working with the PCA9450B? We don't need the GPU and will be disabled by the software.
Best Regards,
Patrick
解決済! 解決策の投稿を見る。
Hi Yuri,
Thanks a lot for your detailled reply.
Is it possible to connect the VDD_DRAM to the VDD_SOC rail as it is on the i.MX8M Nano EVK? For us it is ok to change the schematics because the PCB is not available yet.
Best Regards,
Patrick
@lumen
Hello,
According to Table 4 (PCA9450 selection guide) of the PMIC Datasheet:
- the BUCK3 (VPU/GPU/DRAM) is disabled ;
- LDO4 (0.9 V for VDDA) is OFF by default;
https://www.nxp.com/docs/en/data-sheet/PCA9450DS.pdf
As for i.MX8Mm VPU/GPU/DRAM supply: VDD_VPU and VDD_GPU may be
left unconnected, when not used (Table 36 (i.MX 8M Mini unused power
rail strapping recommendations) of the Hardware Development Guide
for the i.MX8Mm ). But DDR PHY supply voltage VDD_DRAM cannot
be left floating. So, direct replacement of the PCA9450A by
PCA9450B (without VDD_DRAM providing) is not possible.
< https://www.nxp.com/webapp/Download?colCode=IMX8MMHDG >
Regards,
Yuri.
Hi Yuri,
Thanks a lot for your detailled reply.
Is it possible to connect the VDD_DRAM to the VDD_SOC rail as it is on the i.MX8M Nano EVK? For us it is ok to change the schematics because the PCB is not available yet.
Best Regards,
Patrick
@lumen
Hello,
yes, generally it is possible to connect the VDD_DRAM to the VDD_SOC, assuming
the PMIC voltage value is allowed for both VDD_DRAM and VDD_SOC; and current
consumption does not exceed PMIC specs.
Regards,
Yuri.
Hello Yuri,
What changes must be done on BSP side to make the i.MX8M Mini working with the PCA9450B?
Best Regards,
Patrick