I want to control i.MX6's SDMA like following.
Two device is connected on EIM.
one FPGA works as a bus bridge between EIM and low-speed interface. It receive bulk data from low-speed interface intermittently.
I want to use SDMA for low-speed interface to reduce CPU workload. But FPGA does not have a FIFO memory. It can receive only 1 byte. So SDMA speed is limited by low-speed interface. I am afraid of bus busy by burst DMA with low-speed interface.
I have three questions.
1. Can I change burst size of SDMA for EIM?
2. Can I use peripheral DMA for EIM devices?
3. Can FPGA control SDMA access by changing a level of SDMA_EXT_EVENT after SDMA is triggerd?
Best Regards,
Yamaoka
Hello, Yamaoka !
Please use Appendix A (SDMA Scripts) of the i.MX6 Reference Manual about SDMA ROM
scripts and refer to the following about SDMA and EIM.
“imx6 SDMA and EIM bus”
https://community.freescale.com/thread/324491
“i.MX6 maximum EIM burst length and performance”
https://community.freescale.com/docs/DOC-106467
As for Your questions :
1.
> Can I change SDMA burst size for EIM?
For SDMA ROM (mem-to-mem / ap_2_ap) – No.
2.
> Can I use peripheral DMA for EIM devices?
Basically – yes.
3.
> Can FPGA control SDMA access by changing a level of SDMA_EXT_EVENT after SDMA is triggerd?
Please use
“imx6 SDMA and EIM bus”
https://community.freescale.com/thread/324491
Have a great day,
Yuri
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