Hi,
We are using I.MX6 in one of our solutions and I need some clarification regarding "NVCC_PLL_OUT" rail.
In page 554 of IMX6DQRM, it is mentioned that the rail is generated from an internal LDO. Whereas in Sabre-SD board schematic, it is illustrated that the rail is generated using an External LDO.
Kindly refer to the above image for clarity and let me know whether the external LDO is needed.
Generally, for performance, it is better using an external power supply for the PLL. Also, because
of some bugs in old silicon versions the external PLL supply was implemented on the SDP / SDB
designs.
Have a great day,
Yuri
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