LVDS and external clocks

[billwhit]

We have developed a board based on the imx53 qsb, but now we are having a hard time to figure out the programming of clocks for a single LVDS display.  We were unable to use the internal clock, which appeared to be routed from PLL4.  We have set up the display as DI0 and 800x480. 

Our attempts to set the clock to be externally sourced have not worked. We used the settings in ldb.c as well as the devregs utility program to examine and adjust the registers involved (CSCMR2, DI0_GENERAL, IOMUXC_GPR2) but the oscilloscope still shows the same waveform.

Has anyone had any luck with the LVDS displays and external clocks? 

Suggestions on contacts within Freescale or design houses that could help?

Thanks in advance

Bill

[AlisonLuanLOHR1]

Where this change are made? Do you made this change and got any result? I'm facing great troubles to change this value... 

[HenrikJacobsen]

...yes, changing the 2 hard coded "455000000" to < pixclock*7> in ldb.c does it...

[HenrikJacobsen]

...eh, after posting the above question, I guess I figured out the problem: The LVDS serializer clock comes directly from PLL4, and has nothing to do with the pixclock value given in the mode table in ldb.c. Right? So, assuming that PLL4 is not used for anything but the IPU and LDB, I just have to figure out how to change its freq. :)

[HenrikJacobsen]

Hi -

I'm fighting pretty much the same war right now :) The tip with removing tve support was great; with tve, the lvds clock is stuck at 70-somthing MHz. My problem now is: With tve removed, the lvds clock is stuck at 64.998 MHz! Which is the value it should have with pixclock=15385, the value given for "XGA" in ldb.c.

I changed the pixclock value for XGA to 30066 ( and resolution to 800x480), and verified with test output in mxc_ipuv3_fb.c that the pixel rate is set to 33260000l Hz. That's the IPU pixclock... still I have 64.998 MHz on the LVDS connector on the i.MX53-EVK. Something else overriding the clock setting? Any idea will be highly appreciated :)

[TamasMorocz]

Hello Bill,

We faced with the same problem some month ago. We modified the ldb.c for our lcd display, we add a custom fb_videomode entry,  we changed the ldb_clk_prate / pll4_rate  to a proper value but nothing changed. The lvds clock still was about 70 MHz. 

The solution was to remove the tve driver from the kernel (2.6.35). We don't know why but the tve driver overwrites the pll4 clock, when the tve driver/output not enabled.

[sanu]

Thank you  Yamil  Garcia

LVDS is working now

[sanu]

hi

did you tried it in the DI0?

[sanu]

hi

I am using the display port one for LVDS

It already multiplexed with the parallel asynchronus port so only asynchronus display work rather than the sync display

In user guide 18 .DISP0 LCD it is mentioned like this

Be aware that the DI RGB interface is multiplexed with all other asynchronous parallel interfaces.
Therefore, users cannot send data to a synchronous display and another asynchronous parallel display
device at the same time in the same DI. Instead, the i.MX53 sends data to the asynchronous panel (smart
display) while the synchronous interface is inactive (during horizontal and vertical back porch and front
porches). For this reason, the smart display’s frame rate can be affected when multiple displays are
attached to the i.MX53.

[sanu]

hi getting erorr like this

io scheduler cfq registered (default)
mxc_ipu mxc_ipu: Channel already disabled 9
mxc_ipu mxc_ipu: Channel already uninitialized 9
IPU DMFC DP HIGH RESOLUTION: 1(0,1), 5B(2~5), 5F(6,7)
Console: switching to colour frame buffer device 128x48
mxc_ldb mxc_ldb: can't find video mode

[YamilGarcia]

I'm using 20 pins like you.

[YamilGarcia]

Check the explanation to determine the fields of the mxcfb_ldb_modedb

[sanu]

HI

Can send  me the log  so that i can check with mine Where the problem is ?

[sanu]

Have used 20 pin lvds or 30 pin lvds?

I am using 20 pin lvds lcd ?

[sanu]

Hi

How the LDB_CTRL register value setting done .

Do the value are taken from the u-boot command line and assigned to the control register.?

[YamilGarcia]

Yes I have luck with LVDS. This what I did:

First edit the LVDS driver to match your panel timings, the location of the driver is:

/home/lucid/L2.6.35_11.05.01/ltib/rpm/BUILD/linux/drivers/video/mxc/ldb.c

edit the mxcfb_ldb_modedb[] to match your display timings as I show below:

struct fb_videomode mxcfb_ldb_modedb[] = {
 {
  "1080P60", 60, 1920, 1080, 7692,
  100, 40,
  30, 3,
  10, 2,
  0,
  FB_VMODE_NONINTERLACED,
  FB_MODE_IS_DETAILED,},
  /* original */
         /*{
  "XGA", 60, 1024, 768, 15385,
  220, 40,
  21, 7,
  60, 10,
  0,
  FB_VMODE_NONINTERLACED,
  FB_MODE_IS_DETAILED,},*/
         /*LG 17" 60Hz = 13204; 30Hz = 26408*/
         { 
         "XGA", 30, 1280, 768, 26408,
  48, 80,
  2, 13,
  160, 22,
  0,
  FB_VMODE_NONINTERLACED,
  FB_MODE_IS_DETAILED,},       
};

Then set the video kernel parameters as shown below as an example.

video=mxcdi1fb:RGB666,XGA ldb=di1 di1_primary

[sanu]

Hi

could you please help me set this reister value IOMUXC_GPR2