[LTIB 4.0/Yocto BSP 1.5] i.MX6 Display issue on LVDS panel

[charleshuang]

We are using a LVDS to TTL converter between LVDS display port and the TTL panel. (640x480 “24-bit RGB”)

The pixel clock is 85MHZ. (fb_videomode.pixclock = 11764)

I think the clock setting should be no problem. Please refer to the datasheet in the attachment.

I also verified the quality of GUI between Yocto 1.5 and Yocto 1.7.

The Yocto 1.5 also has the same issue as LTIB, but there is no such quality issue on Yoco1.7.

Please tell me how to solve this issue on LTB 4.0 and Yocto BSP 1.5 (3.10.17)

1) Yocto 1.7 (kernel 3.14.28):

  a) U-boot command to enable LVDS output:

setenv mmcargs setenv bootargs console=${console},${baudrate} ${smp} root=${mmcroot} ${bootargs} video=mxcfb0:dev=ldb,640x480M@60,if=RGB24

  b) kernel (Modify dts file):

(No need to modify the code, only the device tree changed)

&ldb {

  ext_ref = "true";

  status = "okay";

  lvds-channel@0 {

  fsl,data-mapping = "jeida";

  fsl,data-width = <24>;

  crtc = "ipu2-di0";

  primary;

  status = "okay";

       display-timings {

            native-mode = <&timing0>;

                 timing0: g070vw01v0 {

                 clock-frequency = <85000000>;

                 hactive = <640>;

                 vactive = <480>;

                 hback-porch = <142>;

                 hfront-porch = <16>;

                 vback-porch = <33>;

                 vfront-porch = <10>;

                 hsync-len = <2>;

                 vsync-len = <2>;

                 };

        };

  };

...

};

2) Yocto 1.5 (kernel 3.10.17):

  a) U-boot command to enable LVDS output:

setenv mmcargs setenv bootargs console=${console},${baudrate} ${smp} root=${mmcroot} ${bootargs} video=mxcfb0:dev=ldb,LDB-KOE,if=RGB24

  b) kernel: Modify ldb.c file

(It’s required to modified ldb.c in order to enable “jedia” option)

       b_1) Add parameters of a new lvds panel in fb_videomode ldb_modedb[]

static struct fb_videomode ldb_modedb[] = {

...

  {

  "LDB-KOE", 60, 640, 480, 11765,

  142, 16,

  33, 10,

  2, 2,

  0,

  FB_VMODE_NONINTERLACED,

  FB_MODE_IS_DETAILED,},

...

}

     b_2) Change LDB_BIT_MAP from SPWG to JEIDA in ldb_disp_init()

...

...

/* TODO: now only use SPWG data mapping for both channel */

  reg &= ~(LDB_BIT_MAP_CH0_MASK | LDB_BIT_MAP_CH1_MASK);

  /* weilun@adv */

+#if 0

+ reg |= LDB_BIT_MAP_CH0_SPWG | LDB_BIT_MAP_CH1_SPWG;

+#else

+ printk("it to JEIDA\n");

+ reg |= LDB_BIT_MAP_CH0_JEIDA | LDB_BIT_MAP_CH1_JEIDA;

+#endif

Thank you.

Original Attachment has been moved to: lvds_info.zip

[igorpadykov]

Hi charles

please try patch provided on

https://community.freescale.com/thread/320314#comments

Best regards

igor

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[charleshuang]

I try your method, but it cannot solve this issue.

Do you have any solution?

Thanks.