LS1028A : net eth0: could not attach to PHY

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LS1028A : net eth0: could not attach to PHY

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Eddy1
Contributor IV

Hi :

I'm using ls1028,on power-on it doesn't detect the PHY. 

Loading Environment from MMC... OK
EEPROM: Read failed.
In: serial
Out: serial
Err: serial
Net: phy init test2
phy init test3
ar8031 test
phy reset 10
Could not get PHY for emdio-3: addr 2

Warning: enetc-0 (eth0) using random MAC address - 22:66:ca:ba:0e:d6
eth0: enetc-0

Then we found that there is no such phy in uboot:

=> mdio list
enetc-0:
emdio-3:
10 - Vitesse VSC8514 <--> swp0
11 - Vitesse VSC8514 <--> swp1
12 - Vitesse VSC8514 <--> swp2
13 - Vitesse VSC8514 <--> swp3
enetc-2:
felix-switch:
=> mdio read swp0 1
Reading from bus emdio-3

But on ls1028ardb, we can see that:

=> mdio list
enetc-0:
emdio-3:
2 - AR8031/AR8033 <--> enetc-0
10 - Vitesse VSC8514 <--> swp0
11 - Vitesse VSC8514 <--> swp1
12 - Vitesse VSC8514 <--> swp2
13 - Vitesse VSC8514 <--> swp3
enetc-2:
felix-switch:

Can you help me solve this problem?

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1 Solution
2,438 Views
bpe
NXP Employee
NXP Employee

u-Boot outputs that message because it does not hear from the PHY on the
management interface. u-Boot obtains the PHY management address and the MDIO bus
it is connected to from the Device Tree. For LS1028A-RDB it is defined here:

https://source.codeaurora.org/external/qoriq/qoriq-components/u-boot/tree/arch/arm/dts/fsl-ls1028a-r...

Your board is probably different in the PHY connection/address/model or the
PHY is not functional. Make sure your u-Boot Device Tree properly reflects
the PHY connection and the PHY responds to MDIO cycles at the specified
address.

 

Best Regards,
Platon

 

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3 Replies
2,439 Views
bpe
NXP Employee
NXP Employee

u-Boot outputs that message because it does not hear from the PHY on the
management interface. u-Boot obtains the PHY management address and the MDIO bus
it is connected to from the Device Tree. For LS1028A-RDB it is defined here:

https://source.codeaurora.org/external/qoriq/qoriq-components/u-boot/tree/arch/arm/dts/fsl-ls1028a-r...

Your board is probably different in the PHY connection/address/model or the
PHY is not functional. Make sure your u-Boot Device Tree properly reflects
the PHY connection and the PHY responds to MDIO cycles at the specified
address.

 

Best Regards,
Platon

 

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2,429 Views
Eddy1
Contributor IV

hi:

Thank you very much. There is indeed interference in the address line.

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2,435 Views
Eddy1
Contributor IV

Hi:

Thank you very much for your reply. The connection of PHY 8033 is the same as that of ls1028ardb, the only difference is the reset signal. I realize that the reset pin(LS1028ARDB) is connected to CPLD, but my schematic diagram is directly connected to CPU with the level conversion chip. Then I also find that when I add reset in uboot code, then the system complains that it can't get PHY for MDIO. When I remove this reset. Sometimes the system can get phyid,sometimes it can't. What is the problem?

Exception log:

init phy sgmii mode
reg:ffff phy_id:ffffffff
reg:ffff phy_id:ffffffff
reg:ffff phy_id:ffffffff
reg:ffff phy_id:ffffffff
reg:ffff phy_id:ffffffff
reg:ffff phy_id:ffffffff
Could not get PHY for emdio-3: addr 2

enetc-0:
emdio-3:
10 - Vitesse VSC8514 <--> swp0
11 - Vitesse VSC8514 <--> swp1
12 - Vitesse VSC8514 <--> swp2
13 - Vitesse VSC8514 <--> swp3
enetc-2:
felix-switch:

normal:

phy init test3
ar8031 test
reg:d074 phy_id:4dd074
803x config test

emdio-3:
2 - AR8031/AR8033 <--> enetc-0
10 - Vitesse VSC8514 <--> swp0
11 - Vitesse VSC8514 <--> swp1
12 - Vitesse VSC8514 <--> swp2
13 - Vitesse VSC8514 <--> swp3
enetc-2:
felix-switch:

my dts:

&enetc0 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&rdb_phy0>;

};

&mdio0 {
status = "okay";
rdb_phy0: phy@2 {
reg = <2>;
};

sw_phy0: phy@10 {
reg = <0x10>;
};
sw_phy1: phy@11 {
reg = <0x11>;
};
sw_phy2: phy@12 {
reg = <0x12>;
};
sw_phy3: phy@13 {
reg = <0x13>;
};
};

I have attached my schematic .

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