Hi,
We have designed a carrier board (based on Variscite IMX8MP DART SOM) with 1 MIPI CSI camera and 1 MIPI DSI display.
When adding support for both camera and DSI display, the display works fine but we are unable to capture frames from the camera (camera driver loads correctly).
If we remove/disable the MIPI DSI display entry from the DTB, we can capture images from the camera.
MIPI DSI Display entry:
/* MIPI-DSI */
&lcdif1 {
status = "okay";
};
&mipi_dsi {
status = "okay";
/* DISPLAY */
panel@0 {
compatible = "techstar,ts8550b";
reg = <0>;
pinctrl-0 = <&pinctrl_mipi_dsi_en>;
reset-gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
dsi-lanes = <2>;
video-mode = <2>;
panel-width-mm = <68>; //TBC
panel-height-mm = <121>; //TBC
status = "okay";
};
};
Camera driver entry:
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
status = "okay";
ov2311_mipi1: ov2311_mipi1@42 {
compatible = "ov2311";
reg = <0x42>;
clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>;
clock-names = "xclk";
/* Disabled CLKO2, since DART-MX8MP camera expansion board uses
* its own oscillator. Enable CLK02 if your desing requres it
*/
#if 0
assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>;
assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
#endif
assigned-clock-rates = <24000000>;
mipi-data-lanes = <2>;
camera-mipi-clk = <832>;
csi_id = <0>;
pinctrl-names = "default";
pwn-gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>;
rst-gpios = <&gpio3 7 GPIO_ACTIVE_LOW>;
mclk = <24000000>;
mclk_source = <0>;
mipi_csi;
status = "okay";
port {
ov2311_mipi1_ep: endpoint {
remote-endpoint = <&mipi_csi0_ep>;
data-lanes = <1 2>;
clock-lanes = <0>;
};
};
};
};
&mipi_csi_0 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
port@0 {
reg = <0>;
mipi_csi0_ep: endpoint {
remote-endpoint = <&ov2311_mipi1_ep>;
data-lanes = <2>;
csis-hs-settle = <13>;
csis-clk-settle = <2>;
csis-wclk;
};
};
};
Are we missing something to use both MIPI CSI and MIPI DSI simultaneously?
Attached dmesg log.
Thanks.
Solved! Go to Solution.
Hi,
We are using a monochrome camera with Y data only. So, we have used ISI. Also, we have a positive improvement.
We changed the sensor mipi clock from continuous to gated clock mode. We can stream the camera and mipi dsi simultaneously now. We are still facing issues in streaming the maximum sensor resolution[1600x1300], but this resolution is not essential for our use case. Thanks for your support.
refer to the logfile, did you use dual camera? could you bring up one camera to the mipi dsi? and what interface do you use? isi or isp? pls share the whole logfile, but you used the third party company source code, I'm not sure what difference between this from nxp bsp, but I can check it
Hi,
We are using only one camera. We removed the other camera entry in the dtb and checked. We are still facing the issue with one camera and mipi dsi setup. We are using isi. Can you specify the logs that you need?
what is your camera format? raw12 bits? pls share your boot up logfile and your whole dts file
Hi,
We are using GREY format configured as RAW8. Attached the log and dts files.
From the log we get "CSIS_DPHYSTATUS[20]: 0x000000c1". From the TRM it means the clock lane is in stop state. In the working scenario, the value is "CSIS_DPHYSTATUS[20]: 0x000000c0". Is there a way to change the clock state?
since you use raw data, why don't use ISP? if you use ISI, you need change the driver and imx8mp couldn't handle raw data directly, otherwise you have operation to handle this
Hi,
We are using a monochrome camera with Y data only. So, we have used ISI. Also, we have a positive improvement.
We changed the sensor mipi clock from continuous to gated clock mode. We can stream the camera and mipi dsi simultaneously now. We are still facing issues in streaming the maximum sensor resolution[1600x1300], but this resolution is not essential for our use case. Thanks for your support.
Hi,
We are using a monochrome camera with Y too,I wonder how you solved the problem in the end。