Hello,
I am using the ITX-P-C444 board which is based upon the i.MX8M. I'm adding two SPI-based GPIO expanders, the max7301, to the board for additional I/O. There is only 1 dedicated chip select line so I'm attempting to use a GPIO pin as one. Using this as reference, I made an addition to the device tree
spi: &ecspi1 {
#address-cells = <1>;
#size-cells = <0>;
fsl,spi-num-chipselects = <1>;
cs-gpios = <0>, <&gpio1 0 9 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
expander0: max7301@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
compatible = "max7301";
spi-max-frequency = <100000>;
status = "okay";
};
expander1: max7301@1 {
#address-cells = <1>;
#size-cells = <1>;
reg = <1>;
compatible = "max7301";
spi-max-frequency = <100000>;
status = "okay";
//fsl,spi-sck-cs-delay = <1>;
};
I built the kernel and two new GPIO controllers appear when I run `cat /sys/kernel/debug/gpio`
However, a problem arrises when I attempt to read data from the chip controller by the GPIO pin. Reading requires two 16 bit packets to be sent with the CS line being flip-flopped between them. The latter isn't happening Looking at the attached images you can see what I mean. The CS line isn't being unasserted between the two consecutive calls in the first image. For reference, the 2nd image has what the CS line should like it in CS0. For some reason, the CS line isn't going up. I've tried to lower the spi frequency thinking that it could be a clock issue but I'm lost. Does anyone have any insight?
