Interfacing i.MX53 to two 4Gb RAM Chips (1GB RAM)

[LeonCraven]

Hi,

Is it possible to interface the i.MX53 to two 4Gb RAM devices, giving a total of 1GB? The Freescale reference designs use four 2Gb devices to give 1GB of RAM. Is there a reason for this?

Looking through the i.MX53 reference manual and comparing the capabilities to Micron's MT41K256M16HA-125 as an example, I don't see any issues; the data width, number of banks, capacity per chip select, column size, address size and burst length all seem to be compatible. Am I missing something?

Has anyone successfully connected 4Gb devices to the i.MX53?

Thanks for your comments in advance!

Cheers,

Leon

[weidong_sun]

Hello,Leon,

      Some customers of ours use the solution you motioned above, But you please pay attention to Chip select (1GB per chip select or 2GB in chip select 0)

      if you use linux BSP, when you debug your board, you should adjust flash_header.S file which is for DDR initialization for you design. This file is at u-boot/board/freescale/mx53_loco/, or u-boot/board/freescale/mx53_smd/

Regards,

weidong

[VenkatRaghavulu]

Hi Weidong,

Can you please attach the correct and update flash_header.S in the community for the above mentioned part number with the considerations of different options of chip select.

Since the file is of great importance and the DDR device specified above is very standard part number, providing the flash_header.S will be of great help. I supposed it does not attract any kind of IP violations.

Can you please attach if these files are with Freescale.

BR,

Venkat.

[weidong_sun]

Hello,Venkat,

    On several i.MX53 EVK board, FSL doesn't use this kind of DDR3 SDRAM, but some of customer use it on their projects based on i.MX53. I don't also have flash_files.S that was adjusted for your DDR3.

    But this work can be done by re-configure memory controller. Only you need to re-configure Address lines(Row address lines and column Address lines , Number of banks)

    Other configurations don't need to be adjusted. When you begin to debug your board, you can tell me and send schematic to me, we can discuss it together.

    My personnal address : weidong.sun@freescale.com

Regards,

Weidong

[weidong_sun]

Hello,Venkat,

     According to your DDR3 datasheet:

The following is for your DDR3 settings in flash_header.S :

...

/*Address: ESDCTL_ESDMISC is 63FD_9000h base + 18h offset = 63FD_9018h*/

/*bit[5]=0(8banks);bit[20]=1(only use CS0 for 2GB address space)*/

MXC_DCD_ITEM(29, ESDCTL_BASE_ADDR + 0x018, 0x00111740) /*Setting ESDCTL Timing Miscellaneous Register(Include CS0,CS1 or only CS0 and Banks)*/

/*28.121.1 ESDCTL Control Register (ESDCTL_ESDCTL)---Address: ESDCTL_ESDCTL is 63FD_9000h base + 0h offset = 63FD_9000h*/

/*bit[26:24}=100(15bit Row address lines); bit[22:20]=001(10bit column address lines*/

MXC_DCD_ITEM(30, ESDCTL_BASE_ADDR + 0x000, 0xc4190000) /*Setting ESDCTL Control Register--CS0,CS1 & ROW & COL address lines*/

.....

Please modify flash_header.S for your design.

In addtion, I found you only use one ODT , ODT1 is not used, So I can't confirm if resistance is OK. if not, you can adjust the following 1 line:

/*Address: ESDCTL_ODTCTRL is 63FD_9000h base + 58h offset = 63FD_9058h*/

MXC_DCD_ITEM(50, ESDCTL_BASE_ADDR + 0x058, 0x00022227) /*Setting ESDCTL_ODTCTRL----PHY ODT Control Register*/

Regards,

Weidong