Imx6 SSI 24Mhz Bit clock generation and 48Khz frame sync clock from pll4

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Imx6 SSI 24Mhz Bit clock generation and 48Khz frame sync clock from pll4

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dp_yanam
Contributor I

we are trying to generate 24Mhz bit clock from SSI 48KHz frame sync clock. When i go through the CCM module & other similar questions in NXP.  mentioned like reprogramming the PLL4 to achieve the bit clock 24Mhz.

Please let me know which part of the code in the kernel reprogram the pll4 in the kernel 4.14.

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dp_yanam
Contributor I

Hi igor,

Thanks for your support & information. i could able to achieve the clock frequency by setting post dividers in the clk_imx6q.c

Best regards,
K. durgaprasad

 

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Durgaprasad

 

simple examples for this case can be found in SDK

https://github.com/RT-Thread/rt-thread/tree/master/bsp/imx6sx/iMX6_Platform_SDK

 

>Please let me know which part of the code in the kernel reprogram the pll4 in the kernel 4.14

 

in linux one can look at clk driver:

https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/clk/imx/clk-imx6q.c?h=imx_4.14.98_...

Documentation

 

Best regards
igor

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