On the EVK for the xx1024, the schematic shows the ENET_CRS_DV pin being routed from the PHY (U11) to the CPU on pin 97 (GPIO_AD_B0_11). The reference manual (p261) says that the ENET_CRS signal must be routed to GPIO_EMC_34.
Is this an error in the eval board? Which pin should this signal be routed to?
Hi,
From RT1024 reference manual page1734 Table 37-44 ENET External Signals description:
ENET_CRS (GPIO_EMS_34 pad) signal only works for MII mode:
RT1024 EVK board ENET works at RMII mode, which using RX_EN (GPIO_AD_B0_11 pad) signal as CRS_DV input signal.
So, the RT1024 EVK board ENET_CRS_DV connection is correct.
best regards,
Mike