IMX6S and PF0100 OTP configuration

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IMX6S and PF0100 OTP configuration

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jamesholland
Contributor I

Hello. I'm reviewing a design that uses a PF0100 PMIC with an MCIMX6S5EVM10C. I can't find any documentation to say which version of the PF0100 is the recommended version, it is not listed in the 'orderable parts' section of the PF0100 datasheet. The datasheet implies that the power up sequence isn't critical as long as VDD_SNVS_IN comes up first and the other supplies are stable when SRC_POR_B is deasserted, yet there are nine different power up configurations available.

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art
NXP Employee
NXP Employee

It depends on the custom schematic, on which power supplies of PF0100 are used to power which domains of the processor etc. Generally, the same (F0) version can be used for i.MX6Solo as for i.MX6Quad/DualLite when following the powering scheme of the i.MX6Quad/DualLite SABRE SD board.


Have a great day,
Artur

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