IMX6 custom MIPI sensor mxc_v4l_dqueue timeout enc_counter 0

[motting]

I would like to use v4l2 to capture video/photo.

My linux kernel is 3.0.35 and the board I am using is SabreLite from Boundary Device.

I am adding an Sony IMX camera which also support MIPI.

I checked the clock signals through oscilloscope and found that 24MHz mclk is present.

Applied Sony provided register settings, the process passed the MIPI "no sensor clk" and "cannot receive data" check.

When I test by running /unit_tests/mxc_v4l2_capture.out -c 1 -iw 2104 -ih 1560 image.raw, it fail at:

     ERROR: v4l2 capture: mxc_v4l_dqueue timeout enc_counter 0

     VIDIOC_DQBUF failed.

I have already matched the MIPI D-PHY clock by mipi_csi2_write(info, 0x00000010, CSI2_PHY_TST_CTRL1);

I tried to set this to a different value but all situations failed at this mxc_v4l_dqueue timeout enc_counter 0.

Could you give me some advice?

[belf26012]

Hi, can you please share your information on how to program the IMX278 ? I'm trying to find the drivers for Linux, with no luck.

Thanks

Francois

[donfreiling]

Hello Motti,

Were you able to get the Sony IMX mipi sensor to work. Questions:

1) Which sensor are you using? (I am working with IMX278 and IMX230)

2) Could you post a zip file with the driver source you are using?

3) Does your module include a VCM driver?

Regards,
Don

[belf26012]

Hi did you receive an answers for this ?

Thanks

[saurabh206]

Hi

Check attached document.

This will help to debug MIPI.

[motting]

Hi Saurabh,

I followed the debug guide till the end.

All the settings are correct.

Could you give me some advice what else I should check?

Motti

[motting]

The MIPI D-phy state I received is jumping 0x200 and 0x2b0 and error1 = error 2 = 0.

Which is different from the debug guide.

Is this the root cause?

What is the meaning of 0x200 / 0x2b0 in MIPI D-phy state?

[motting]

Having checked the RM, MIPI D-phy state defines as below.

32-12: Reserved

11-0:

bypass_2ecc_tst

phy_stopstateclk

phy_rxulpsclknot

phy_rxclkactivehs

phy_stopstatedata_3

phy_stopstatedata_2

phy_stopstatedata_1

phy_stopstatedata_0

phy_rxulpsesc_3

phy_rxulpsesc_2

phy_rxulpsesc_1

phy_rxulpsesc_0

For MIPI D-phy state=0x2b0 that I received, phy_rxclkactivehs = 1, which indicates that the clock lane is actively receiving a DDR clock.

That means MIPI clock can be received to my board.

[igorpadykov]

also one can check IOMUXC_GPR register,  if the CSI input

is from the parallel pins or from the MIPI pins:

https://community.freescale.com/thread/390183

~igor

[motting]

In my driver I have already set "CSI input from the MIPI pins" by setting bit 19/20 of IOMUXC_GPR register 1.

My driver is modified from another existing MIPI driver so the CSI setting is likely correct.

But still I am getting no frame buffer.