The spreadsheet/script in https://community.freescale.com/docs/DOC-94917 sets MDPDC bit7 SLOW_PD=0 indicating fast precharge PD mode, yet the MR0 value written to the DRAM sets bit12=0 indicating slow precharge PD. The TRM states in the description of MDPDC SLOW_PD that it should be set the same as memory (which makes sense). Therefore I believe the spreadsheet/script to be in error.
Does Freescale have any recommendations on if the values should be set to fast precharge PD or slow?
Regards,
Tim
Solved! Go to Solution.
Sorry for pending a long time.
The configuration should be aligned on both controllor and DDR device side.
Fast or slow mode should depend on real application, that's a trage off between power consumption and working efficiency.
Thanks for digging it out!
Sorry for pending a long time.
The configuration should be aligned on both controllor and DDR device side.
Fast or slow mode should depend on real application, that's a trage off between power consumption and working efficiency.
Thanks for digging it out!
Had Involved design team.
Due to NPI urgent schedule, will check this question next week.
Suppose getting update before end of next week.