IMX6 1588 ENET_REF_CLK on GPIO_16

[zlxie]

Hi Sir,

   I'm debugging 1588 issues on our imx6solo (P/N: MCIMX6S5EVM10AC) system. RGMII is used on our system. I have configures GPIO_16 as MX6QDL_PAD_GPIO_16__ENET_REF_CLK signal based on the thread from  https://community.nxp.com/thread/326497 .

   The strange thing is that the GPIO_16 pin will output 50MHz clock after eth0 up. If use "ifconfig eth0 down" command, the 50MHz clock output will disappear. I use "memtool" tool to check the register  (IOMUXC_SW_MUX_CTL_PAD_GPIO16, address 0x020E0214), the values is 0x02, for ENET_REF_CLK.

if (IOMUXC_SW_MUX_CTL_PAD_GPIO16, address 0x020E0214) is changed other value except 0x02, there is no the 50MHz clock output from the GPIO_16 PIN when eth0 up.

   I can't provide refer clock on GPIO_16 pin because it will conflict with the 50MHz output. If there is no extern reference clock, the 1588 can't work. How to fix this issue? Thanks.

Best regards

Zhenlei Xie

[zlxie]

After I remove the extern reference clock, GPIO_16 always output 50MHz clock. I can get 1PPS signal output on GPIO_19 pin. But the 1pps signal on GPIO_19 can't sync to the 1588 master. The phase  difference between GPIO_19 1 PPS output and1588 master 1pps will be more than 10 millisecond.

[weidong_sun]

Dear Zhenlei ,

   GPIO_16 pin has been used for 125MHz output by default ( I checked it in linux bsp version 4.9.88).

1. In arch/arm/boot/dts/imx6qdl-sabresd.dtsi

        pinctrl_enet: enetgrp {
            fsl,pins = <
                MX6QDL_PAD_ENET_MDIO__ENET_MDIO        0x1b0b0
                MX6QDL_PAD_ENET_MDC__ENET_MDC        0x1b0b0
                MX6QDL_PAD_RGMII_TXC__RGMII_TXC        0x1b030
                MX6QDL_PAD_RGMII_TD0__RGMII_TD0        0x1b030
                MX6QDL_PAD_RGMII_TD1__RGMII_TD1        0x1b030
                MX6QDL_PAD_RGMII_TD2__RGMII_TD2        0x1b030
                MX6QDL_PAD_RGMII_TD3__RGMII_TD3        0x1b030
                MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL    0x1b030
                MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
                MX6QDL_PAD_RGMII_RXC__RGMII_RXC        0x1b030
                MX6QDL_PAD_RGMII_RD0__RGMII_RD0        0x1b030
                MX6QDL_PAD_RGMII_RD1__RGMII_RD1        0x1b030
                MX6QDL_PAD_RGMII_RD2__RGMII_RD2        0x1b030
                MX6QDL_PAD_RGMII_RD3__RGMII_RD3        0x1b030
                MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL    0x1b030
               /* MX6QDL_PAD_GPIO_16__ENET_REF_CLK    0x4001b0a8 */
            >;

if you don't use it, comment it, please!

2. In  drivers/clk/imx/clk-imx6q.c

 static void __init imx6q_clocks_init(struct device_node *ccm_node)

...

   /*Set enet_ref clock to 125M to supply for RGMII tx_clk */

    clk_set_rate(clk[IMX6QDL_CLK_ENET_REF], 125000000);

...

}

If you don't need internal reference clock, and external PHY can provide the clock for SYNC with MAC, Connect 125MHz output on your PHY to ENET_REF_CLK pin, please! (see schematic of mx6qsabreSDB board)

Hope above information can help you!

Have a nice day!

BR,

Weidong