IMX UL boot configuration pin status for NAND boot media

[vineethhegde]

Hi,

Am designing i.MX UL processor based board. The media is NAND Flash.

I got the following info from the Ref manual of UL processor.

There are 24 Boot Configuration Pins(BOOT_CFG1[7:0],BOOT_CFG2[7:0],BOOT_CFG3[7:0]). I found only the status of BOOT_CFG1[7:0] for NAND Boot. 

Please let me know the what should be the status(Pull up/Pull down) of BOOT_CFG2[7:0],BOOT_CFG3[7:0] during board boot. 

Regards,

Vineeth 

[igorpadykov]

Hi Vineeth 

NAND boot configuration is given in Table 8-10. NAND Boot eFUSE Descriptions,
pin state after reset is described in Table 95. 14x14 mm Functional Contact
Assignments i.MX6DQ Datasheet
http://cache.freescale.com/files/32bit/doc/data_sheet/IMX6DQCEC.pdf

Best regards
igor
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[brunoferrarezi]

Hi,

Could you check the information about the Table 95? I didnt find It on IMX6DQCEC.. Tablet 95 refer HSIC Transmit Parameters.