How to modify or disable the memory interleaving access mode on the imx8qm board?

[wangbo9105]

I noticed in the fsl_stc.h header file of the SCFW that the interface STC_RIL_SetInterleave(STC_Type *base, stc_interleave_mode_t interleave) can be used to modify or disable the memory interleaving access mode. Is that correct?

(1) How do I use this interface, and where in the board.c file of the SCFW should I call it to modify the memory interleaving access mode?

(2) When using the STC_RIL_SetInterleave function to modify the memory interleaving access mode, do I need to call other related interfaces beforehand to ensure a successful setting?

(3) After setting the interleaving access mode using the STC_RIL_SetInterleave function, can I verify if the setting was successful by reading the INTERLEAVE_SEL member variable in the STC_Type struct?

typedef struct {

__IO uint32_t INTERLEAVE_SEL;

...

} STC_Type;

(4) After disabling the memory interleaving access mode using STC_RIL_SetInterleave on the imx8qm board, how do the two DDR controllers work when accessing memory subsequently?

[pengyong_zhang]

Hi @wangbo9105 

Here is our expert reply:

==================================================

1. I think only STC 15 can be set successfully is reasonable, because subsystem 15 is SC_SUBSYS_DB, which is the subsystem of DRAM block. 

./platform/config/mx8qm/soc.h:166:#define SC_SUBSYS_DB        15U

2. The RVSD_HPR_ENABLE is register for "Highest Priority Request scheduler enable", which is used for QoS. so it has no relation with INTERLEAVE_SEL. And there is no external document about STC registers, since it's not expected to be modified by customer.

3. The SCFW will call the function as board_qos_config(SC_SUBSYS_DB), so that's why the ss value is always 15. But when you call function STC_RIL_SetInterleave, the ss value is actually not used. So it's not directly related. But indeed, only subsystem 15 (DRAM block) should be able to configure the interleaving mode, and it's already verified by you

==================================================

[wangbo9105]

Hi, @pengyong_zhang 

Thank you very much for your and your experts' replies!

Could I ask you a few more questions?

==============================================================================
(1) Regarding subsystem 15, I'd like to clarify: I meant the 15th STC.

Here's the code that successfully sets the interleaving mode:

/****** code ******/
STC_Type *base_ptrs[] = STC_BASE_PTRS;
stc_interleave_mode_t interleave = kSTC_InterleaveNone;

STC_Type *base = base_ptrs[14];
STC_RIL_SetInterleave(base, interleave);
/****** code ******/

In the file src/scfw_export_mx8qm_b0/platform/devices/MX8QM/MX8QM.h, there's a definition :

#define STC14_BASE (0x5c720000)

We know that the base address of STC14 is 0x5c720000.

So, is STC14 the one that controls the memory interleaving mode for SC_SUBSYS_DB, as your experts mentioned "because subsystem 15 is SC_SUBSYS_DB, which is the subsystem of DRAM block."?
Since I didn't express myself clearly before, could you please confirm again that STC14 is responsible for controlling the memory interleaving mode of SC_SUBSYS_DB?

(2) There are 16 STCs in IMX8QM. Are all the remaining 15 STCs, except for STC14, unable to set the memory interleaving mode?
Because in the IMX8QMRM.pdf manual, under the 1.2.1.2 DRAM Block (DB) section, I saw the settings for memory interleaving mode.
I want to confirm if only the STC of DB can be set, and the other 15 STCs cannot.

(3) My requirement is to disable the memory interleaving mode on A53/A72.
I don't want the operating system running on A53/A72 to alternately use two memory controllers.
Can I disable it? Or is there another way to achieve this?

(4) Is disabling the interleaving mode also an operation on the STC corresponding to A53/A72?
Does A53/A72 correspond to STC5? Or what is the corresponding STC number?

I have not found the corresponding relationship in the IMX8QMRM.pdf manual.

(5) If the memory interleaving mode can be disabled for A53/A72, how will A53/A72 use the memory controllers?

==============================================================================

I'm eagerly looking forward to your answers!

[pengyong_zhang]

Hi @wangbo9105 

you shouldn't change STC settings unless it's really necessary. But if you want to try it anyway, you should change it in the board_qos_config() function in board.c file like following:

void board_qos_config(sc_sub_t ss)
{
    /* This function is to allow NXP support or professional services to
     * perform such optimization for a customer or application. It is not
     * intended for direct customer use.
     */
    STC_Type *base_ptrs[] = STC_BASE_PTRS;
    stc_interleave_mode_t interleave = kSTC_InterleaveNone;

    for (uint32_t inst = 0U; inst < FSL_FEATURE_SOC_STC_COUNT; inst++)
    {
        STC_Type *base = base_ptrs[inst];
        STC_RIL_SetInterleave(base, interleave);
    }
}

[wangbo9105]

Hi, @pengyong_zhang 

Thank you for your reply!

The code and location I wrote are as you described. The function board_qos_config() normally won't be entered unless ss_updown_db(SC_PGP_XXX, 0x1); is called.

I have found an issue:

(1) I speculate that the implementation of STC_RIL_SetInterleave is as follows:

void STC_RIL_SetInterleave(STC_Type *base, stc_interleave_mode_t interleave)
{
if (base == NULL ) {
return;
}

interleave &= 0x3;
base->INTERLEAVE_SEL = interleave;
}

After I used your code to disable the memory interleaving mode for 16 STC instances, I read the value of base->INTERLEAVE_SEL. Only subsystem 15 (base->INTERLEAVE_SEL=0x3) was set successfully. For the other subsystems, base->INTERLEAVE_SEL=0x0 failed to set, but base->RVSD_HPR_ENABLE=0x3. I don't know why it was set to RVSD_HPR_ENABLE. What is the relationship between INTERLEAVE_SEL and RVSD_HPR_ENABLE?

Could you please provide a manual describing the STC registers?

(2) When entering the board_qos_config(sc_sub_t ss) function, the value of ss is always 15. Does this mean only subsystem 15 can reconfigure the memory interleaving mode?

I am eagerly looking forward to your response!

[pengyong_zhang]

Hi, @wangbo9105 

This function STC_RIL_SetInterleave is a SCFW internal function, and not for customer to use. So customer shouldn't use this function to change the STC settings.

In the initialization stage of SCFW, it will set STC to the optimized settings for i.MX8QM architecture. These settings cannot be changed in the runtime. The STC interleave is set to kSTC_Interleave4K in current settings. 

In short, the STC settings is already optimized for i.MX8QM and customer should leave it for SCFW to take care of it.

B.R

[wangbo9105]

Hi,@pengyong_zhang

Thank you very much for your reply.

I also found a similar question in the forum, and the link is:

https://community.nxp.com/t5/i-MX-Processors/How-to-use-STC-RIL-SetInterleave-function-in-SCFW/m-p/1...

However, when I use the function STC_RIL_SetInterleave in src/scfw_export_mx8qm_b0/platform/board/mx8qm_mek/board.c, I don't know where to modify it to make it take effect?

[pengyong_zhang]

Hi @wangbo9105 

The same question link you can not access, The feature is enabled bt DDR PHY register, So i do not think it can be disabled by the SW.

And which SCFW do you use?

[pengyong_zhang]

Hi, @wangbo9105 

I found the same question about interleaving with you, Hope it can help you.

B.R

[wangbo9105]

Hi, @pengyong_zhang
Thank you very much for your response. Could you please provide me with the link or manual source for this same question?

Also, could you please tell me why I cannot use the function STC_RIL_SetInterleave in the board.c of SCFW to disable the memory interleaving mode, and what are the reasons and implications?

[pengyong_zhang]

Hi, @wangbo9105 

Please be patient, Still working on your issue. And will give you the feedback ASAP.

B.R

[wangbo9105]

Can you provide me with a sample code snippet that demonstrates how to modify the memory interleaving mode?