Please refer to the Section 5.2 "Clock Control Module (CCM)", especially, to the sub-sections 5.2.4 "Clock Tree", 5.2.7.3 "CCGR Interface" and 5.2.8 "CCM Memory Map/Register Definition", of the i.MX7 Reference Manual document. As it can be
seen, each particular clock in the clock tree has its own Clock Control and Gating Register (CCGM). Each register contains 4 identical 2-bit fields that control the particular clock gating depending on the particular power mode, as defined in the Table 5-17. Each of the 4 fields is dedicated to the corresponding Resource Domain, as defined in the Resource Domain Controller module, refer to the Section 3.2 "Resource Domain Controller (RDC)" of the document above for more details. For simplicity, it is possible to assign the equal clock resources to all power domains, i.e. write all 4 fields of a single CCGR equally. So, for particular clock, write the following values to the CCGR fields depending on the clock gating requirements.
00 clock is always gated
01 clock runs in Run mode only
10 clock runs in Run and Wait modes
11 clock always runs regardless of the power mode
The mapping of a CCGR registers to a particular clocks is listed in the Table 5-19 of the document above.
Have a great day,
Artur
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