How to interpret System Clocks table in iMX6 RMs?

[MichaelV]

What is the meaning of the System Clocks table in the iMX6 RMs?

What is the clock in the "Clock" column?

If we would change source or  frequency of for instance the AHB clock, would we need to gate all gates listed in the "Gating CCM_CCGR" bits that have ahb_clk_root in front in the "Clock Root" column? (for AHB on iMX6SDL this would mean gating AIPS_TZ1, ARM_DBG, ASRC, CAAM_SECURE_MEM, CAAM_WRAPPER_CLK, ENET, ESAI, GPU2D, GPU3D, HDMI_TX_ISFR, IPU1_IPU, MIPI_CORE, MLB, OCRAM, ROM, USBOH3 and USDHC1..4).

In iMX6SDL look at EPDC in the table. It shows:

+----------+--------+---------------------+--------------------+--------------------+

|  Block   |        |       Clock         |  Gating CCM_CCGR   | Override CCM_CMEOR |

| Instance | Clock  |        Root         |        bits        |        bits        |

+----------+--------+---------------------+--------------------+--------------------+

|  EPDC    | pixclk |  epdc_pix_clk_root  | ipu_di1_clk_enable |                    |

+----------+--------+---------------------+--------------------+--------------------+

|          | aclk   |  epdc_axi_clk_root  | ipu_ipu_clk_enable |                    |

|          |        |  pxp_axi_clk_root   |                    |                    |

+----------+--------+---------------------+--------------------+--------------------+

How does this correspond to the Clock Tree diagram, or the Clock Root Generator diagrams?

There is no mention of CCGR3 [11-10 CG5] epdc_pix_clk_enable and CCGR3 [7-6 CG3] epdc_axi_clk_enable, but I'm sure those gates affect epdc_pix_clk_root and epdc_axi_clk_root...

The information that I'm after is Clock Signal -> CGs, in other words; which gates depend on which clock signals. I know there can be more gates per clock signal. I just need a clear diagram of where those gates are (in something like a clock tree diagram), or a location where I can filter that information from (like the iMX6 Platform SDK maybe?).

Thanks!

[igorpadykov]

Hi Michel

regarding:

"change source or  frequency..AHB clock, would we need to gate all gates listed in the "Gating CCM_CCGR"

bits that have ahb_clk_root in front in the "Clock Root" column?"

not, it is not necessary to gate. It may be recommended just to disable modules

which somehow use this clock.

Clock gating epdc_axi_clk_root  is circle "CG" depicted on p.810

Figure 18-6 IMX6SDLRM i.MX 6Solo/6DualLite Applications Processor Reference Manual

CCGR3 [11-10 CG5] epdc_pix_clk_enable corresponds to epdc_pix_clk_root gating

and CCGR3 [7-6 CG3] epdc_axi_clk_enable to epdc_axi_clk_root

I am not sure that any additional diagrams can be provided.

For changing clock frequencies it may be also useful to look at

EB790 Configuration of Phase Fractional Dividers

Best regards

chip

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[MichaelV]

So, is the table wrong?

Why does it list ipu_di1_clk_enable and ipu_ipu_clk_enable in the gate bit column for epdc?

I know the (CG) circles indicate gates, but figure 18-6 doesn't show all gates for all signals: where is the VDO_AXI gate? Where is the PCIE gate? etc.

So, we have a System Clock table that is unclear (or containing wrong information, or missing information) and we have Clock Root Generator diagrams that are containing wrong information (see my other posts) and are missing gate information for a lot of signals, and we have an iMX6 Platform SDK that is containing wrong (old) information. How are we going to be able to develop a proper BSP when all this basic information is missing?

The EPDC I mentioned in my original post is just an example of the information I need.

I need a definitive source of information showing all the CLOCK SIGNAL to CLOCK GATE mappings.

[igorpadykov]

Hi Michel

yes, these seems as misprints.

I think you can help to improve documentation by entering SR ticket for each error.

Special team is gathering these errors and next release of RM will fix them.

Best regards

chip