How to change Duty of LSCLK of i.MX25

取消
显示结果 
显示  仅  | 搜索替代 
您的意思是: 
已解决

How to change Duty of LSCLK of i.MX25

跳至解决方案
1,372 次查看
yuuki
Senior Contributor II

Dear all,

We connect an LCD panel to i.MX25.
LSCLK is 44.3MHz.

A frequency is 44.3MHz of the set value.

However, Duty is not 50%.

Please see the following figure.

LCDC_LSCLK.png

Is there the method to change Duty of LSCLK to 50%?
We referred to a reference manual, but were not able to find the method.

Best Regards,
Yuuki

标签 (1)
标记 (2)
0 项奖励
回复
1 解答
1,268 次查看
igorpadykov
NXP Employee
NXP Employee

Hi Yuuki

duty cycle is not configurable but it can be improved

by using dividers as even numbers (preferably as 2**N) for both

LCDC pixel clock rate divider and LCDC_CLK (PER DIV7).

Also increasing drive strength of clock pad may slightly

improve waveform.

Best regards

igor

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. Thank you!

-----------------------------------------------------------------------------------------------------------------------

在原帖中查看解决方案

0 项奖励
回复
3 回复数
1,269 次查看
igorpadykov
NXP Employee
NXP Employee

Hi Yuuki

duty cycle is not configurable but it can be improved

by using dividers as even numbers (preferably as 2**N) for both

LCDC pixel clock rate divider and LCDC_CLK (PER DIV7).

Also increasing drive strength of clock pad may slightly

improve waveform.

Best regards

igor

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. Thank you!

-----------------------------------------------------------------------------------------------------------------------

0 项奖励
回复
1,268 次查看
yuuki
Senior Contributor II

Dear Igor-san,

Thank you for your support.

We generate LSCLK=44.3MHz from AHB=133MHz.
At this case, we set PERDIV7=0(divided by 1) and PCD=2(divided by 3).

Changing AHB frequency affects the whole system.
Therefore we cannot change the AHB frequency, and PERDIV7 or PCD cannot set even numbers.

In addition, is there the method?

If there is not a method, we have to examine an LCD panel allowing this clock Duty.
Would you tell me the theoretical value of LSCLK Duty in the following setting?

May I have advice?

Best Regards,
Yuuki

0 项奖励
回复
1,268 次查看
igorpadykov
NXP Employee
NXP Employee

Hi Yuuki

duty cycle is not configurable, there are no methods

for its changing.

Best regards

igor

0 项奖励
回复