Dear all,
I have an i.MX53 evk board and a standard BSP for the board, now I want to know how to calculate the frequnce of the UART & DDR, for example, there may be some registers in CCM & PLL modules specify the frequence, can anyone tell me what's the registers and how to calculate the frequence? Thank you very much.
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Hi, Chengwu
You need to read register CCM_CSCMR1[25-24] to see what is the UART's clock source, PLL1 or PLL2 or PLL3 or LPAPM, then you need to read these PLLx's register to see what are their frequence. For PLL, there is formula to calculate their freq, in RM chapter 21.3.2.4. For LPAPM, it should be 24MHz from OSC, you need to see CCM_CCSR[10] to see whether it is from OSC or PLL4. Then you will know what is the freq of UART. But, you need to be aware of there is divider in CCM_CSCDR1 for UART, PRE and PODF, you need to divided both PRE and PODF divider. The BSP should already support reading such clock's rate directly from clk API, clk_get_rate, you can just call it to get UART's rate.
Same for DDR, first, get its parent's freq, then div by its divider, you can look up register description in CCM chapter.
Hi, Chengwu
You need to read register CCM_CSCMR1[25-24] to see what is the UART's clock source, PLL1 or PLL2 or PLL3 or LPAPM, then you need to read these PLLx's register to see what are their frequence. For PLL, there is formula to calculate their freq, in RM chapter 21.3.2.4. For LPAPM, it should be 24MHz from OSC, you need to see CCM_CCSR[10] to see whether it is from OSC or PLL4. Then you will know what is the freq of UART. But, you need to be aware of there is divider in CCM_CSCDR1 for UART, PRE and PODF, you need to divided both PRE and PODF divider. The BSP should already support reading such clock's rate directly from clk API, clk_get_rate, you can just call it to get UART's rate.
Same for DDR, first, get its parent's freq, then div by its divider, you can look up register description in CCM chapter.
Thank you very much.
Hi,
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