How do you set a GPIO pin to tri-state in software or on the command line (linux)?

[amberworth]

Having trouble finding a way to set a GPIO on the imx8 to tri-state.

Is there a way to configure a GPIO pin as output with a value of tristate?

If no, will configuing a pin as an input be effectively the same?

[amberworth]

I am working with both an imx8mn and an imx8mp.  For this example, I'd like to stick with the imx8mp.

In the IMX8MPRM section 8.2.2.1 GPIO pad features, it lists 3-state and open-drain output as a feature.

Is that controlled by the PE and PS pins mentioned in 8.2.2.1.1?

Will configuring a GPIO output with PE = 0(disable) put a pad into 3-state?

[BiyongSUN]

I think you mentioned is the following in reference manual. 

It is not a capability, it is silicon design. 

As reference  manual says, i.MX has 3-state and open drain output.  

3-state and open-drain output are two type of the output.

It is silicon design. By default i.MX  pin/pad is   3-state output.

If you need open-drain output, you need to set the IOMUX register. 

 3-state output in i.MX is cmos output. I believe, it is very typical silicon design. shown in datasheet. 

and you also can find on internet everywhere.  

Pins have a three-state logic. If no device is enabled, then the pins are in high impedance state. It means that the output driver is not controlling the state of a connected circuit.

If you set IOMUX as alt GPIO  and GPIO is input. there is no output path. 

For the input path, it is high impedance, that is it could be an "input".

That is why most of pin/pad default alt is GPIO and the GPIO default is input. 

Silicon designer designs this to make the chip default high impedance on I/O.

you also can see in the linux, it will change the pin/pad to gpio make it high impedance during the suspend to avoid some power leaking.

When no output path, the PMOS and NMOS are both open. 

BTW, the pull up/pull down is on the right side of the CMOS. 

For the open-drain, it is not silicon default, you need to set it. 

It is easy to do, the settings for open-drain is just disconnect the PMOS. 

open-drain 

&fec {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_fec>;
pinctrl-1 = <&pinctrl_fec_sleep>;
phy-mode = "rmii";
status = "okay";
};

pinctrl_fec: fecgrp {
fsl,pins = <
MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0
MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0
MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0
MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0
MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0
MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0
MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0
MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0
MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8
>;
};

pinctrl_fec_sleep: fecgrp-sleep {
fsl,pins = <
MX6SL_PAD_FEC_MDC__GPIO4_IO23 0x3080
MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x3080
MX6SL_PAD_FEC_RXD0__GPIO4_IO17 0x3080
MX6SL_PAD_FEC_RXD1__GPIO4_IO18 0x3080
MX6SL_PAD_FEC_TX_EN__GPIO4_IO22 0x3080
MX6SL_PAD_FEC_TXD0__GPIO4_IO24 0x3080
MX6SL_PAD_FEC_TXD1__GPIO4_IO16 0x3080
MX6SL_PAD_FEC_REF_CLK__GPIO4_IO26 0x3080
>;

[igorpadykov · Accepted solution]

for pad settings one can look for example in sect.8.2.4.153 SW_PAD_CTL_PAD_GPIO1_IO00 SW PAD Control Register  (IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00)  i.MX 8M Plus Applications Processor Reference Manual

There is no tri-state capability, as alternative one can select ODE - Open Drain or

configure it as input.

Best regards
igor

[igorpadykov]

Hi Amber

what is processor full part number used in the case, In general pad capabilities, like

tri-state, open drain and others can be found in Chapter IOMUX Controller (IOMUXC) each

processor reference manual, look for "IOMUXC_SW_PAD_CTL_PAD_xyz". In linux

one can change this pad register using memtool

https://source.codeaurora.org/external/imx/imx-test/tree/test/memtool?h=lf-5.10.52_2.1.0

Best regards
igor