HDMI Pixel clock frequency 170000 kHz is not supported

[yuklin_soo]

Hi there,

On my side, I noticed an issue that when booting up an IMX8MQ EVK board with a Yocto Linux image of kernel version 4.9.88 programmed into an SD card, there is no video output from the HDMI interface, and running the command “dmesg” shows below kernel error messages:

[    8.253446] [drm] mode:1920x1080p75, pixel clock 170000 kHz

[    8.259248] [drm] Pixel clock frequency: 170000 kHz, character clock frequency: 170000, color depth is 8-bit.

[    8.269686] [drm:phy_cfg_t28hpc] *ERROR* This pixel clock frequency (170000 kHz) is not supported.

[    8.279044] [drm:hdmi_phy_init_t28hpc] *ERROR* failed to set phy pclock

[    8.285869] [drm:imx_hdp_bridge_mode_set] *ERROR* Failed to initialise HDP PHY

The pixel clock frequency of 170000 kHz is read from the EDID inside the display monitor connected to the HDMI interface of the IMX8MQ EVK board,

[    9.638122] i.mx8-hdp 32c00000.hdmi: imx_hdp_connector_get_modes: 0,ff,ff,ff,ff,ff,ff,0

[    9.638125] imx_hdp_connector_get_modes: EDID version 1.3

[    9.643636] imx_hdp_connector_get_modes: detailed timing 0 pixel clock 170000 khz

[    9.651285] imx_hdp_connector_get_modes: detailed timing 0 horizontal active 1920 pixels

[    9.659490] imx_hdp_connector_get_modes: detailed timing 0 vertical active 1080 pixels

[    9.667628] imx_hdp_connector_get_modes: detailed timing 1 pixel clock 148500 khz

[    9.675222] imx_hdp_connector_get_modes: detailed timing 1 horizontal active 1936 pixels

[    9.683425] imx_hdp_connector_get_modes: detailed timing 1 vertical active 1080 pixels

[    9.691458] imx_hdp_connector_get_modes: detailed timing 2 pixel clock 0 khz

[    9.698672] imx_hdp_connector_get_modes: detailed timing 3 pixel clock 0 khz

The pixel clock frequency 170000 kHz is currently not supported in the HDP PHY initialization function when pixel_clk_from_phy == 1.  Besides, it looks like the following list of pixel clock frequencies are possibly not supported by the driver also:  119MHz, 88.75MHz, 108MHz, 71MHz, 40MHz, 36MHz, 30.24MHz, 25.175MHz, 28.32MHz, 75MHz, 65MHz, 148.352MHz, 27.027MHz, 74.176MHz, 25.2MHz, 74.176MHz, and 185.580MHz

To verify the functionality of the HDMI video output, the only workaround I can think of is to modify the pixel clock frequency to a supported frequency 148.5MHz before calling the hdmi_phy_init_t28hpc() function, and then the HDMI video output is working properly.

In the function imx_hdp_mode_setup(),

/* mode set */  

mode->clock = 148500;     < ============

ret = imx_hdp_call(hdp, phy_init, &hdp->state, mode, hdp->format, hdp->bpc);

if (ret < 0) {

        DRM_ERROR("Failed to initialise HDP PHY\n");

        return;

}

imx_hdp_call(hdp, mode_set, &hdp->state, mode,

             hdp->format, hdp->bpc, hdp->link_rate);

Currently, we are looking for a way to support pixel clock frequency of 170MHz and 185.58MHz for our monitors, and I think it's required to update the function phy_cfg_t28hpc() in file API_AFE_t28hpc_hdmitx.c 

However, we do not know how to work with the registers: cmnda_pll0_ip_div, cmn_ref_clk_dig_div, pll_feedback_divider_total, cmnda_pll0_fb_div_*, cmnda_hs_clk_*

Is there any guidelines, documentations, or specifications that can help?

[pawel_kopalko]

Hi

we are having same issue with technexion board, it seems that all available boards be it nxp's or other vendors have the same problem. On imx6 in such situation we can set only_cea module parameter in kernel args to overcome not supported frequency.

Some solution would be really appreciated since a lot of people is having the same issue. For the time being running 1920p dell monitor is fine but we can't show any demo to our client like that since it's silly (full digital cluster development)

Regards,

Pawel.

[pawel_kopalko]

Actually no. At some point in time (limux bsp relese from nxp) the display started to work (the 1920x720) but the other 1280x800 wasn't detected... so in short no it's still a lottery. I just hope this will be resolved as imx8 will get more mature

[eng201]

Thanks, I did end up trying a different kernel and eventually got it working but now I have audio issues :smileysad:

[weidong_sun]

Hello Alex,

    Can you print out the edid block with adding code to function of "hdmi_get_edid_block"? Then i.MX Expert  will help to  debug with your edid.

Have a nice day!

Best Regards,

NXP TIC Weidong Sun

[weidong_sun]

Any update?

[yuklin_soo]

Hi Wigros,

Actually, I have provided the EDID blocks print out in the previous message, however, to print out the EDID blocks in my display monitor, I modified the function imx_hdp_connector_get_modes() instead of the function hdmi_get_edid_block().

The output contains only pixel clock frequency, horizontal active, and vertical active, and is as shown below:

1. Base block

[ 9.643636] imx_hdp_connector_get_modes: detailed timing 0 pixel clock 170000 khz
[ 9.651285] imx_hdp_connector_get_modes: detailed timing 0 horizontal active 1920 pixels
[ 9.659490] imx_hdp_connector_get_modes: detailed timing 0 vertical active 1080 pixels

2. Extension block

[ 9.667628] imx_hdp_connector_get_modes: detailed timing 1 pixel clock 148500 khz
[ 9.675222] imx_hdp_connector_get_modes: detailed timing 1 horizontal active 1936 pixels
[ 9.683425] imx_hdp_connector_get_modes: detailed timing 1 vertical active 1080 pixels

The EDID version is 1.3. Please let me know if you need more details.

[weidong_sun]

Hello Alex,

    see source code below, please!

int hdmi_get_edid_block(void *data, u8 *buf, u32 block, size_t len)
{
    HDMITX_TRANS_DATA edidResp;
    state_struct *state = data;
    CDN_API_STATUS ret = 0;

    memset(&edidResp, 0, sizeof(edidResp));
    switch (block) {
    case 0:
        ret = CDN_API_HDMITX_READ_EDID_blocking(state, 0, 0, &edidResp);
        break;
    case 1:
        ret = CDN_API_HDMITX_READ_EDID_blocking(state, 0, 1, &edidResp);
        break;
    case 2:
        ret = CDN_API_HDMITX_READ_EDID_blocking(state, 1, 0, &edidResp);
        break;
    case 3:
        ret = CDN_API_HDMITX_READ_EDID_blocking(state, 1, 1, &edidResp);
        break;
    default:
        pr_warn("EDID block %x read not support\n", block);
    }

   /* add these 2 lines here, please! */

    for (int i =0; i < edidResp.len; i < 0)
        printk("%02x", edidResp.buff[i]);

...

}

Then send me print result, please!

Have a nice day!

Best regards,

Weidong

[yuklin_soo]

Hi,

The print result is shown below -

1. EDID base block raw data:

00 ff ff ff ff ff ff 00 04 72 45 05 17 7b 10 62 15 1a 01 03 80 3c 22 78 2a ba 25 a3 56 50 a0 28 0e 50 54 b3 0c 00 b3 00 95 00 81 80 81 00 81 c0 71 4f 01 01 01 01 68 42 80 6a 70 38 27 40 08 20 98 04 56 50 21 00 00 1a 02 3a 80 18 71 38 2d 40 58 2c 45 00 56 50 21 00 00 1e 00 00 00 fd 00 30 4b 1e 53 12 00 0a 20 20 20 20 20 20 00 00 00 fc 00 41 63 65 72 20 4b 47 32 37 30 0a 20 20 01 ad

2. EDID extension block raw data:

02 03 27 f1 4b 01 02 03 04 90 05 11 12 13 14 1f 23 09 07 01 83 01 00 00 65 03 0c 00 10 00 68 1a 00 00 01 01 30 4b e6 02 3a 80 18 71 38 2d 40 58 2c 45 00 56 50 21 00 00 1e 8c 0a d0 8a 20 e0 2d 10 10 3e 96 00 56 50 21 00 00 18 01 1d 00 72 51 d0 1e 20 6e 28 55 00 56 50 21 00 00 1e 8c 0a d0 90 20 40 31 20 0c 40 55 00 56 50 21 00 00 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01

[weidong_sun]

Hello Alex,

     I have sent an email to you, and included members of i.MX Expert team, let us discuss it in email. if you received email, reply it , please!

Have a nice day!

Best Regards,

Weidong

[erickhemphill]

Weidong,

We are experiencing a very similar issue with our imx8m. We are attempting to get an 800x480 display working via the TI TFP401, which requires a 32 MHz pixel clock. I have tested some changes to imx-hdp.c (adding the mode line parameters) and encounter the following:

[ 21.741501] Pixel clock frequency: 32000 kHz, character clock frequency: 32000, color depth is 8-bit.
[ 21.750906] This pixel clock frequency (32000 kHz) is not supported.
[ 21.757453] VCO frequency is 1 kHz
[ 21.761025] Current vco_freq (1 kHz) is not supported.

I noted that 27 MHz is a supported pixel clock freqency, and re-built with that value - which actually dumps garbage onto the display, though at what appears to be the 720x480 (VIC 3). This would make some sense as the TI TFP401 does not have a scaler.

So I am wondering the same thing as Alex - is there any documentation for the registers described in phy_cfg_t28hpc() in API_AFE_t28hpc_hdmitx.c to achieve the desired clock rate?

The EDID block for our display (reported by the imx8 by modifying hdmi_get_edid_block):

00 ff ff ff ff ff ff 00 04 81 04 00 01 00 00 00 01 11 01 03 80 0f 0a 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 80 0c 20 80 30 e0 2d 10 28 30 d3 00 6c 44 00 00 00 18 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00  00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 17

Any help would be appreciated.

[quyenngo]

Dear Wigros,

I meet the same problem with imx8M Emcraft board. Please help me to fix it.

Very best regards.

[yuklin_soo]

Hi Weidong,

I have already received your email and I will try to get back to you as soon as possible.

Thank you for the help.

Regards,

Alex