Generating pin_mux files for Apalis I.MX8QM - Cortex M4

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Generating pin_mux files for Apalis I.MX8QM - Cortex M4

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Florin101
Contributor II

Hi everyone,

I kindly ask for your help with generating the mux files for Cortex M4_1 for my Apalis i.MX8QM. The current version of the NXPConfigurator (V15) has limited support i.MX8QM (SDK_2_9_0_MIMX8QM6xxxFF]. The  i.MXConfigurator (V14) is in a similar situation. The header files generated are significantly different from those included in the hello_world example:

/***********************************************************************************************************************
* Definitions
**********************************************************************************************************************/

 

/* UART0_RTS_B (number AU45), BB_UART2_RX/J20A[28] */
/* Routed pin properties */
#define BOARD_INITPINS_BB_UART2_RX_PERIPHERAL DMA__UART2
/*!< Peripheral name */
#define BOARD_INITPINS_BB_UART2_RX_SIGNAL uart_rx
/*!< Signal name */
#define BOARD_INITPINS_BB_UART2_RX_PIN_NAME UART0_RTS_B
/*!< Routed pin name */
#define BOARD_INITPINS_BB_UART2_RX_PIN_FUNCTION_ID SC_P_UART0_RTS_B
/*!< Pin function id */
#define BOARD_INITPINS_BB_UART2_RX_LABEL "BB_UART2_RX/J20A[28]" /*!< Label */
#define BOARD_INITPINS_BB_UART2_RX_NAME "BB_UART2_RX" /*!< Identifier */
 
Versus
 

/***********************************************************************************************************************

 

* Definitions

 

**********************************************************************************************************************/

 

/* UART0_RTS_B (number AU45), BB_UART2_RX/J20A[28] */

#define BOARD_INITPINS_BB_UART2_RX_PIN_FUNCTION_ID IMX8QM_UART0_RTS_B /*!< Pin function id */

These lack of details generates errors at build.

In general, what are the plans for providing full support for this flagship SoM?

Many thanks,

Florin 

 

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