Enabling 4 Gb in uboot build for i.MX6Q

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Enabling 4 Gb in uboot build for i.MX6Q

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frankmiller
Contributor IV

I'm trying to enable 4 Gb of DRAM in uboot.

I've made the following changes in ltib/rpm/BUILD/u-boot-2009.08/include/configs/mx6q_sabresd.h

/*-----------------------------------------------------------------------

* Physical Memory Map

*/

//#define CONFIG_NR_DRAM_BANKS  1

#define CONFIG_NR_DRAM_BANKS    4

#define PHYS_SDRAM_1            CSD0_DDR_BASE_ADDR

#define PHYS_SDRAM_1_SIZE       (1u * 1024 * 1024 * 1024)

#define PHYS_SDRAM_2            CSD0_DDR_BASE_ADDR

#define PHYS_SDRAM_2_SIZE       (1u * 1024 * 1024 * 1024)

#define PHYS_SDRAM_3            CSD0_DDR_BASE_ADDR

#define PHYS_SDRAM_3_SIZE       (1u * 1024 * 1024 * 1024)

#define PHYS_SDRAM_4            CSD0_DDR_BASE_ADDR

#define PHYS_SDRAM_4_SIZE       (1u * 1024 * 1024 * 1024)

//#define iomem_valid_addr(addr, size) \

//      (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))

#define iomem_valid_addr(addr, size) \

        (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_4 + PHYS_SDRAM_4_SIZE))

Do these look right?  What should I be using for as a replacement for CSD0_DDR_BASE_ADDR for banks 2-4?

If I make these changes will they be propagated to the kernel or do I need to make changes there too?

Thanks,

FM


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frankmiller
Contributor IV

Finally got all this to work.  There are a couple of steps.  First you modify flash_header.S to get you address decoding to work.  That's very board dependent and not addressed here.

Second you setup the memory map in u-boot.  This is what we did to get it working:

/*-----------------------------------------------------------------------

* Physical Memory Map

*/

#define CONFIG_NR_DRAM_BANKS    2

#define PHYS_SDRAM_1            0x10000000

#define PHYS_SDRAM_1_SIZE       (8u * 0x10000000)

#define PHYS_SDRAM_2            0x80000000

#define PHYS_SDRAM_2_SIZE       ((8u *0x10000000) - 4)

#define iomem_valid_addr(addr, size) \

        (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_4 + PHYS_SDRAM_4_SIZE))


Couple things to note here.  First PHYS_SDRAM_1 is 0x10000000 rather than 0 since ARM reserves the lower 256MB for various things.  The u-boot and kernel code handle this with this value set  despite the PHYS_SDRAM_SIZE_1 being 2 GB.


Second, note the - 4 on the end of PHYS_SDRAM_SIZE_2.  This is needed I think since somewhere in the kernel, these two sizes are added and since they exceed 0xffffffff, the result is 0 and the kernel won't boot.


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frankmiller
Contributor IV

Also, I found these in ltib/rpm/BUILD/u-boot-2009.08/include/asm-arm/arch-mx6/mx6.h:

#define MMDC0_ARB_BASE_ADDR         0x10000000
#define MMDC0_ARB_END_ADDR          0x7FFFFFFF
#define MMDC1_ARB_BASE_ADDR         0x80000000
#define MMDC1_ARB_END_ADDR          0xFFFFFFFF


/* Legacy Defines */

#define CSD0_DDR_BASE_ADDR              MMDC0_ARB_BASE_ADDR

#define CSD1_DDR_BASE_ADDR              MMDC1_ARB_BASE_ADDR

I'm not sure why these are defined this way.  Shouldn't CSD0_DDR_BASE be 0 and CSD1_DDR_BASE be 0x40000000?  And then some CSD2_DDR_BASE be 0x80000000 and CSD3_DDR_BASE be 0xc0000000?

Thanks,

FM


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frankmiller
Contributor IV

Finally got all this to work.  There are a couple of steps.  First you modify flash_header.S to get you address decoding to work.  That's very board dependent and not addressed here.

Second you setup the memory map in u-boot.  This is what we did to get it working:

/*-----------------------------------------------------------------------

* Physical Memory Map

*/

#define CONFIG_NR_DRAM_BANKS    2

#define PHYS_SDRAM_1            0x10000000

#define PHYS_SDRAM_1_SIZE       (8u * 0x10000000)

#define PHYS_SDRAM_2            0x80000000

#define PHYS_SDRAM_2_SIZE       ((8u *0x10000000) - 4)

#define iomem_valid_addr(addr, size) \

        (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_4 + PHYS_SDRAM_4_SIZE))


Couple things to note here.  First PHYS_SDRAM_1 is 0x10000000 rather than 0 since ARM reserves the lower 256MB for various things.  The u-boot and kernel code handle this with this value set  despite the PHYS_SDRAM_SIZE_1 being 2 GB.


Second, note the - 4 on the end of PHYS_SDRAM_SIZE_2.  This is needed I think since somewhere in the kernel, these two sizes are added and since they exceed 0xffffffff, the result is 0 and the kernel won't boot.


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frankmiller
Contributor IV

In addition to setting up the Chip Selects, I ultimately had to do a detailed calibration of the DDR3 RAM against the 1.2 GHz Quad core part.  I ended up having to go through this interesting procedure with the calibration tool.

First, I put the memory parameters into the DDR3 spreadsheet provided by Freescale.

I used the calibration values from this spreadsheet to seed the DDR3 calibration tool.  I then ran the tool and got new calibration values.  I took the output of this tool and fed the values back into the inputs of a second run of the tool.  I did this several times until I discovered that output values were converging.  I then took the converged output values and used them in the u-boot code for calibration and voila, the 4 GB of RAM has worked like a charm since.  I hope this helps you.

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soujanyak
Contributor I

Hello ,

I am trying to enable 2GB DDR3 in uboot ( MT41K256M16 – 32 Meg x 16 x 8 banks ) only single chip select,

I've made the following changes in include/configs/mx6q_sabresd.h

Also my data is 16bit addressable:

#define CONFIG_NR_DRAM_BANKS    8

#define PHYS_SDRAM_1            CSD0_DDR_BASE_ADDR

#define PHYS_SDRAM_1_SIZE       (32u * 0x1000 *0x1000)

#define PHYS_SDRAM_2            CSD0_DDR_BASE_ADDR + PHYS_SDRAM_1_SIZE

#define PHYS_SDRAM_2_SIZE       (32u * 0x1000 *0x1000)

#define PHYS_SDRAM_3            CSD0_DDR_BASE_ADDR + PHYS_SDRAM_2_SIZE

#define PHYS_SDRAM_3_SIZE       (32u * 0x1000 *0x1000)

#define PHYS_SDRAM_4            CSD0_DDR_BASE_ADDR + PHYS_SDRAM_3_SIZE

#define PHYS_SDRAM_4_SIZE       (32u * 0x1000 *0x1000)

#define PHYS_SDRAM_5            CSD0_DDR_BASE_ADDR + PHYS_SDRAM_4_SIZE

#define PHYS_SDRAM_5_SIZE       (32u * 0x1000 *0x1000)

#define PHYS_SDRAM_6            CSD0_DDR_BASE_ADDR + PHYS_SDRAM_5_SIZE

#define PHYS_SDRAM_6_SIZE       (32u * 0x1000 *0x1000)

#define PHYS_SDRAM_7            CSD0_DDR_BASE_ADDR + PHYS_SDRAM_6_SIZE

#define PHYS_SDRAM_7_SIZE       (32u * 0x1000 *0x1000)

#define PHYS_SDRAM_8            CSD0_DDR_BASE_ADDR + PHYS_SDRAM_7_SIZE

#define PHYS_SDRAM_8_SIZE       (32u * 0x1000 *0x1000)

#define iomem_valid_addr(addr, size) \

        (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_8 + PHYS_SDRAM_8_SIZE))

Kindly confirm Are my configurations correct?

Thanks

Soujanya.K

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