ERROR FOUND, we can't get suitable value !!!!

[孙金凯]

My design is the same as the development board（SABRESDP_DESIGNFILES）！

Can you help analyze and solve the issue，thanks！

============================================
DDR Stress Test (2.6.0)
Build: Aug 1 2017, 17:33:18
NXP Semiconductors.
============================================

============================================
Chip ID
CHIP ID = i.MX6 Solo/DualLite (0x61)
Internal Revision = TO1.4
============================================

============================================
Boot Configuration
SRC_SBMR1(0x020d8004) = 0x00001040
SRC_SBMR2(0x020d801c) = 0x1a000001
============================================

ARM Clock set to 1GHz

============================================
DDR configuration
BOOT_CFG3[5-4]: 0x00, Single DDR channel.
DDR type is DDR3
Data width: 64, bank num: 8
Row size: 14, col size: 10
Chip select CSD0 is used
Density per chip select: 1024MB
============================================

Current Temperature: 40
============================================

DDR Freq: 396 MHz

ddr_mr1=0x00000004
Start write leveling calibration...
running Write level HW calibration
Write leveling calibration completed, update the following registers in your initialization script
MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x001F001F
MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x003A0044
MMDC_MPWLDECTRL0 ch1 (0x021b480c) = 0x00300034
MMDC_MPWLDECTRL1 ch1 (0x021b4810) = 0x002D0045
Write DQS delay result:
Write DQS0 delay: 31/256 CK
Write DQS1 delay: 31/256 CK
Write DQS2 delay: 68/256 CK
Write DQS3 delay: 58/256 CK
Write DQS4 delay: 52/256 CK
Write DQS5 delay: 48/256 CK
Write DQS6 delay: 69/256 CK
Write DQS7 delay: 45/256 CK

WARNING: write-leveling calibration value is greater than 1/8 CK.
Per the reference manual, WALAT must be set to 1 in the register MDMISC(0x021B0018).
This has been performed automatically.
However, in addition to updating the calibration values in your DDR initialization,
it is also REQUIRED change the value of MDMISC in their DDR initialization as follows:

MMDC_MDMISC (0x021b0018) = 0x00011740

Starting DQS gating calibration
. HC_DEL=0x00000000 result[00]=0x11111111
. HC_DEL=0x00000001 result[01]=0x00000011
. HC_DEL=0x00000002 result[02]=0x00000011
. HC_DEL=0x00000003 result[03]=0x00000011
. HC_DEL=0x00000004 result[04]=0x11111111
. HC_DEL=0x00000005 result[05]=0x11111111
. HC_DEL=0x00000006 result[06]=0x11111111
. HC_DEL=0x00000007 result[07]=0x11111111
. HC_DEL=0x00000008 result[08]=0x11111111
. HC_DEL=0x00000009 result[09]=0x11111111
. HC_DEL=0x0000000A result[0A]=0x11111111
. HC_DEL=0x0000000B result[0B]=0x11111111
. HC_DEL=0x0000000C result[0C]=0x11111111
. HC_DEL=0x0000000D result[0D]=0x11111111
ERROR FOUND, we can't get suitable value !!!!
dram test fails for all values.

Error: failed during ddr calibration

[igorpadykov]

Hi 金凯 孙 

some errors are described in Freescale i.MX6 DRAM Port Application Guide-DDR3 

DQS gating calibration error "can't get suitable value"

may be caused by board noise, so one can check hardware using

IMX6DQ6SDLHDG, Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applic...

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[孙金凯]

It may be caused by faulty welding！

Press the chip（DDR） with my finger to calibrate it and successed！

[孙金凯]

We have verified this conclusion！DDR虚焊造成的！