EPDC "TCE underrun" with high resolution 3200x1200 on DualLite sabresd evaluation kit

[yitelee]

BSP: ICS 4.0.4 + EINK patch to enable EPDC functionality.

target board: SABRESD + DualLite  evaluation kit

Hi Guys~

I am using DualLite on E-Reader product, I got a problem when i replace panel parameters to my target resolution, 3200(source)x1200(gate), 85Hz FrameRate

then error message "imx_epdc_fb imx_epdc_fb: TCE underrun! Will continue to update panel" shown on the console print

, I have no idea how to solve this issue, can anyone help?

I only replace the setting used for E060SCM panel as following

struct fb_videomode
.name	"e060scm_mode"
.refresh	85
.xres	3200
.yres	1200
.pixclock	240000000
.left_margin	16
.right_margin	693
.upper_margin	12
.lower_margin	8
.hsync_len	16
.vsync_len	12
.sync	0
.vmode	FB_VMODE_NONINTERLACED
.flag	0

struct mxc_epdc_fb_mode
struct fb_videomode *mode	&e060scm_mode
vscan_holdoff	10
sdoed_width	10
sdoed_delay	20
sdoez_width	10
sdoez_delay	20
GDCLK_HP	1707
GDSP_OFF	1350
GDOE_OFF	0
gdclk_offs	186
num_ce	2

[Bio_TICFSL]

Hi Yite,

TCE Underrun in EPDC, is caused by a corner condition: when the LUT[n] finished waveform loading but still working on WB processing, the LUT[n+1:15] waveform loading will be hold. It will be triggered when the working buffer processing time for LUT[n] spans over 2 blanking periods.

One frame scan of data will be corrupted on the frame in which the TCE underrun occurred. All subsequent frames will be correct.

The issue may be resolved by implementing one or all of the below workarounds: 1. When update is submitted, ensure the LUT acquires a higher LUT number than current active LUTs. — Order— LUT[0], LUT[1], LUT[15] — If LUT[15] is in use, TCE Underrun could still occur if new update is sent. 2. Ignore TCE Underrun IRQ — If TCE Underrun occurs, EPD hardware will continue to complete the update. — On frame where TCE Underrun occurs, the frame's data will be corrupted. All pixels will receive the last value in the FIFO. The rest of frames for an update are accurate. 3. Time update request with Frame End IRQ — If the update is submitted to the EPD, just after the VSCAN hold off, it will allow for ~2 full frames or over 23.4 mS to complete WB preprocessing for an 85-Hz panel. 4. Increase DRAM bandwidth to ensure the working buffer processing finishes within 1 frame scan. — For example, if the TCE Underrun occurs when the DRAM clock = 160 MHz, increase the DRAM clock to 200 MHz.

Latest Android BSPs versions implemented the workaround already. However looks like is not implemented to 4.0.x

Hope this helps.

[cbg1]

Hello Bio_TICFSL,

Pls send me the patch also. i am facing this issues now. 

Thanks,

Brian

[nobuyukihayama]

Hello Bio_TICFSL

Do you have this patch for ICS?

or, If you know where is this patch download, pls let me know.

If you don't have this patch, do you have source code that is included this workaround? ( this is not for ICS ), please give it to me.
If I get it, I can confirm difference.

Best Regards

nob

[Rita_Wang]

Hello Yite Lee,

Which version BSP are you using? The BSP in freescale website?

Have a nice day

Best Regards

Dan

[yitelee]

Dear Dan,

Android 13.4.1 BSP  (which support Android 4.0.4 ICS)

It is an old version currently not available on the website, this is from product which used before.

Thx.