Dual Rank DDR3 SODIMM

[smiller2]

We have an existing design running a single rank DDR3 SODIMM  on a iMX6SoloX.   We are respinning the board and wonder about supporting dual rank DIMMs since the customer wants more memory.   The processor has only a single DDR3 clock output. 

1. Is there a recommended solution for buffering this single clock output to drive multiple loads?

2. I am confused as to the number of ODT signals supported.  The datasheet lists two, but my schematic symbol only has one on pin U3.   (Perhaps the original creator of the symbol only entered the one that he needed. )  Does the SoloX have two ODTs?   If not, then what is the recommended way to attach the ODT of the second rank?

3.  I remember some of the processors were pin compatible.  Is there a better pin compatible solution to the iMX6SoloX that would get better processing power and a better memory interface?

Thanks.

[gusarambula]

Hello Stephen Miller,

The i.MX6SX has one chip select when in DDR3 mode. However, you may have two chips connected to the same clock, similarly to the i.MX6SX SABRE board (link to the schematic below, you may need to login to download this file).

https://www.nxp.com/webapp/Download?colCode=IMX6SOLOX-SABRESDB-DESIGNFILES&appType=license

As for the ODT signals, it may be one or two depending on the package you are using. The MAPBGA 19x19 0.8mm has two ODT signals, the MAPBGA 17x17 0.8mm and MAPBGA 14x14 0.65mm only have one. If you are unsure of pin assignments, especially since the documentation may be confusing in this regard, I would recommend using the Pins Tool for i.MX (link below).

https://www.nxp.com/design/designs/pins-tool-for-i-mx-application-processors:PINS-TOOL-IMX

As for migrating to a different i.MX processor, the i.MX6 Solo is the closest one. You may find the following Application Note (AN4815, link below) useful, albeit in the reverse way as you plan to migrate to the i.MX6XS or a bigger i.MX processor like the i.MX6Solo.

 https://www.nxp.com/docs/en/application-note/AN4815.pdf

Once you are working on the realm of the i.MX6S, it’s possible to design a PCB that allows to switch from i.MX6S to i.MX6D or i.MX6Q. Please see Application Note 4397 (link below) for more detail.s

https://www.nxp.com/docs/en/application-note/AN4397.pdf

My apologies for the inconvenience! I hope this information helps!

Regards,

[smiller2]

The comment about one chip select in DDR3 is confusing.  I never heard this restriction before.  I have an Excel spreadsheet from NXP that calculates register settings for initializing the DDR3 memory.  If I set that spreadsheet for two chip selects, then it generates Mode Register settings for both chip selects.  If I set it for one chip select, then the mode register setting of the second chip select is commented out.    I never tried running both chip selects.  However we do have it connected up in the system and we thought it would be a future upgrade path.

In trying to get more DDR3 memory available for our end customer,  I am limited by the fact that we are using the 17X17 BGA.  In that package, the DDR address line A15 is not connected to any package pin.   So, I cannot fully use 64K Row Address memory.   The present DRAM we are using is 32K Row and 1K column. There are some devices that are 64K row Address and 2K Column address.   I could double the memory for the customer if used a bigger DRAM and just discarded 1/2 of the memory since I cannot control A15.  (It is tied low at the device.)   However, to do that, the Solox would have to support 2K column addresses.  This means it needs to skip A10 and use column address A0-A9 and A11.  Does the NXP support that mode?  

Are there any lists of qualified DDR3 DRAM with each type of NXP processor?

Thanks for all the help.

----- Steve