Display pixel clock limitation to 74.25 MHz

[sebastian1]

Hi,

I'm using a board with the IMX8 SoC and 4.14.98 IMX kernel.

I'm trying to add support for a MIPI-DSI display (800x480@60Hz) that needs a pixel clock of ~25MHz.

The problem is that there is a minimum limit for the pixel clock of 74.25MHz, both in the LCDIF and DCSS driver.

In the drivers there is mentioned a TODO about fixing this minimum limit.

https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/gpu/drm/mxsfb/mxsfb_drv.c?h=imx_4....
https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/gpu/imx/dcss/dcss-dtg.c?h=imx_4.14...

Any plans or timeline on fixing this clock limit?

Thank you!

[sebastian1]

Hi Santiago,

Could you please show me the patch you worked to allow dsi_lanes = 1?

Thank you!

[sotero]

Hi Sebastian. For enabling support for 1 lane you have to patch drivers/gpu/drm/bridge/nwl-dsi.c:

@@ -664,7 +655,7 @@ static bool nwl_dsi_bridge_mode_fixup(struct drm_bridge *bridge,
 
        DRM_DEV_DEBUG_DRIVER(dsi->dev, "lanes=%u, data_rate=%lu\n",
                             config->lanes, config->bitclock);
-       if (config->lanes < 2 || config->lanes > 4)
+       if (config->lanes < 1 || config->lanes > 4)
                return false;

Maybe the lines numbers are not the same in your linux kernel sources. At this moment I'm using linux-imx_4.19.35_1.1.0. This experimental kernel version from NXP already has all the patches about the pixelclock limitations.

[sebastian1]

Hi Santiago,

I was doing this obvious modification as well, but I was under the impression that it doesn't work.

In fact it was working but I was measuring the wrong signal.

Thank you for your help!