DDR3 access error

[shojigoto]

Hello community,

We have a problem in executing u-boot which seems to be caused by DDR3 access error.

DDR Stress Tester passes up to 640MHz, but when I download the program to the DDR via JTAG ICE,

it sometimes returns verify error.

Could it happen in the conditions where DDR Stress Test is passing?

Regards,

Shoji

[BiyongSUN]

Have you applied the calibration result to the JTAG init script?

[igorpadykov]

Hi Shoji

DDR Stress Test has much tighter tests than uboot. Probably in this

case some board/ddr initialization was skipped, like pads drive strength

or specific processor settings (for example some parts may run only up to 800MHz).

Also uboot can be run in ldo or ldo-bypass mode, recommended to start with

ldo mode.

Best regards

igor

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[shojigoto]

Hello igor,

Thank you for your reply.

I am using the init script for i.Mx6Q DDR3 prepared in the ddr_stress_tester_v2.10\script\mx6dq folder

and edit it for the ICE. So I think that DDR3 init script is same in both DDR Stress Test and the ICE download.

Could you tell me where some board/ddr initialization process is done in the DDR Stress Tester?

[igorpadykov]

Hi Shoji

how did you test memory: read/write memory with jtag

(Uboot may already use this memory address) ?

Please try with uboot command: mtest.

Also had you adjusted uboot/../include/configs/*.h board file

with board memory size.

~igor

[shojigoto]

Hello igor,

I tested DDR3 with uboot mtest command on the 8 boards(our custom boards).

Some boards fails in executing uboot and some boards returns mtest errors.

It seems to be caused by problems in accessing DDR3.

On the other hand, I observe that mtest is passing on 8 boards using the DDR3 init script for the reference board(SabreSD) as it is, which is "DDR_Stress_Tester_v2.30\ddr_stress_tester_v2.30\script\mx6dq\MX6Q_SabreSD_DDR3_1GB_64bit.inc".

I also found the DDR3 initialization Script Generation Aid at https://community.freescale.com/docs/DOC-105963.

By editting specific register values we are able to obtain the same file with the above-mentioned "MX6Q_SabreSD_DDR3_1GB_64bit.inc".

Modified registers are as follows:

1) tAOFPD   (0x021B0008) ：8.5(original) --> 0.1～3.7 (modified)

2)  tAONPD   (0x021B0008) ：8.5 -->1.9～3.7

3) tWR         (0x021B0010) ：15 --> 134～135

4) MR0: DLL (0x021B001C) ：1 --> 9

The original settings are matched with our DDR3 datasheet, but the above modification is made for "MX6Q_SabreSD_DDR3_1GB_64bit.inc".

Our observation shows these modfication should have critical influence on stable DDR3 performance on our boards.

I would like to clarify why SabreSD init script is OK and our calibrated script is causing errors.

Regards,

Shoji

[igorpadykov]

Hi Shoji

MX6Q_SabreSD_DDR3_1GB_64bit.inc was produced for

MT41K128M16JT memories used on Sabre boards. With other type

of memory script may be different, depending on memory datasheet timings.

If your board uses MT41K128M16JT, then issue may be caused by layout,

one can try to tweak drive strength in processor and memory.

Best regards

igor