DDR test fail "dram test fails for all values"

[nickruan]

We produce some iMx6Q boards, some board always fail to download image, the other boards can download successfull.

About the boards with errors, we are testing DDR with ddr_stree_tester_v2.6, but the tool report the error.

============================================
        DDR Stress Test (2.6.0)
        Build: Nov 18 2016, 23:40:32
        NXP Semiconductors.
============================================

============================================
        Chip ID
CHIP ID = i.MX6 Dual/Quad (0x63)
Internal Revision = TO1.5
============================================

============================================
        Boot Configuration
SRC_SBMR1(0x020d8004) = 0x00003860
SRC_SBMR2(0x020d801c) = 0x21000011
============================================

ARM Clock set to 1GHz

============================================
        DDR configuration
BOOT_CFG3[5-4]: 0x00, Single DDR channel.
DDR type is DDR3
Data width: 64, bank num: 8
Row size: 14, col size: 10
Chip select CSD0 is used
Density per chip select: 1024MB
============================================

Current Temperature: 32
============================================

DDR Freq: 396 MHz

ddr_mr1=0x00000004
Start write leveling calibration...
running Write level HW calibration
Write leveling calibration completed, update the following registers in your initialization script
    MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x00160017
    MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x00190013
    MMDC_MPWLDECTRL0 ch1 (0x021b480c) = 0x0013001B
    MMDC_MPWLDECTRL1 ch1 (0x021b4810) = 0x0009001B
Write DQS delay result:
   Write DQS0 delay: 23/256 CK
   Write DQS1 delay: 22/256 CK
   Write DQS2 delay: 19/256 CK
   Write DQS3 delay: 25/256 CK
   Write DQS4 delay: 27/256 CK
   Write DQS5 delay: 19/256 CK
   Write DQS6 delay: 27/256 CK
   Write DQS7 delay: 9/256 CK

Starting DQS gating calibration
. HC_DEL=0x00000000    result[00]=0x01111111
. HC_DEL=0x00000001    result[01]=0x00110011
. HC_DEL=0x00000002    result[02]=0x00000011
. HC_DEL=0x00000003    result[03]=0x00000011
. HC_DEL=0x00000004    result[04]=0x11111111
. HC_DEL=0x00000005    result[05]=0x11111111
. HC_DEL=0x00000006    result[06]=0x11111111
. HC_DEL=0x00000007    result[07]=0x11111111
. HC_DEL=0x00000008    result[08]=0x11111111
. HC_DEL=0x00000009    result[09]=0x11111111
. HC_DEL=0x0000000A    result[0A]=0x11111111
. HC_DEL=0x0000000B    result[0B]=0x11111111
. HC_DEL=0x0000000C    result[0C]=0x11111111
. HC_DEL=0x0000000D    result[0D]=0x11111111
ERROR FOUND, we can't get suitable value !!!!
dram test fails for all values.

Error: failed during ddr calibration

What's means about the log? what's reasons may cause this problems?

Thanks,

[Yuri]

Hello,

   According to section 3.3.1 (Identifying Issue on Calibrations) of “Freescale i.MX6 DRAM Port Application
Guide-DDR3”:

  There is a chance that there is an error during the calibration, it may fail to find a valid delay window
for some particular bytes. If the tool fails to find a valid window for a byte, it would be a good idea to
fine tune the drive strength of both DQS and DQ of that byte. Ideally, the drive strength should match
the trace impedance. If the information is not available, you could increase or decrease the drive
strength and see if there is any improvement. If there is still no improvement after changing the drive
strength, it should be the time to check the PCB layout. Design rules can be found in “HW Design
Checking List for i.Mx6”.

Freescale i.MX6 DRAM Port Application Guide-DDR3 

  Recent design checklist "HW_Design_Checking_List_for_i.MX6DQP6DQ6SDL"
may be found at:

https://community.nxp.com/docs/DOC-93819 

Have a great day,

Yuri

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[nickruan]

Yuri,

Thank you for your replay.

How to tune the drive strength to match the trace impedance?

BRs

Nick

[Yuri]

Hello,

  please look at the following 

https://community.nxp.com/message/562332 

Regards,

Yuri.