DDR Stress test fails on IMX7S

[jjamesson]

Hi, NXP Community,

I am having problems with executing DDR stress test on my custom board hosting an IMX7S and the Micron MT52L256M32D1PF LPDDR3. I have managed to configure the DDR enough to run U-boot and Linux kernel correctly without any problems so far, but the DDR stress tests just fail.

I have tried the GUI version on Windows and the U-boot/JTag versions on Linux. Moreover, they fail at different places. On the GUI version, the test simply fails. On the U-Boot/Jtag version, the test just freezes after a certain point (see log below).

I have tried changing the DDR frequencies, chip density, and played around with different settings but the results are pretty much similar. Also, manually writing to and reading from memory works.

Maybe someone has an idea to why this happens?

Thank you in advance,

James

--------------------------------------------------------------------------------------------------------------------------

I have attached the logs for both the GUI DDR stress test and U-Boot stress test results below.

GUI:

============================================
DDR Stress Test (3.0.0)
Build: Dec 14 2018, 14:13:33
NXP Semiconductors.
============================================

============================================
Chip ID
CHIP ID = i.MX7 Dual (0x72)
Internal Revision = TO1.3
============================================

============================================
Boot Configuration
SRC_SBMR1(0x30390058) = 0x00002800
SRC_SBMR2(0x30390070) = 0x09000001
============================================

============================================
DDR configuration
DDR type is LPDDR3
Data width: 32, bank num: 8
Row size: 15, col size: 10
One chip select is used
Density per chip select: 1024MB
Total density is 1024MB
============================================

DDR Stress Test Iteration 1
DDR Freq: 300 MHz
t0.1: data is addr test
Address of failure(step2): 0x80000000
Data was: 0x8006c000
But pattern should match address
Error: failed to run stress test!!!

U-Boot:

=> go 0x00910000
## Starting application at 0x00910000 ...

============================================
DDR Stress Test (3.0.0)
Build: Dec 14 2018, 14:21:26
NXP Semiconductors.
============================================

============================================
Chip ID
CHIP ID = i.MX7 Dual
Internal Lots = 0x30360800
============================================

============================================
Boot Configuration
SRC_SBMR1(0x30390058) = 0x00002800
SRC_SBMR2(0x30390070) = 0x0a000001
============================================

What ARM core speed would you like to run?
Type 1 for 800MHz, 2 for 1GHz
ARM Clock set to 1GHz

============================================
DDR configuration
DDR type is LPDDR3
Data width: 32, bank num: 8
Row size: 15, col size: 10
One chip select is used
Density per chip select: 1024MB
Total density is 1024MB
============================================

Please select the DDR density per CHANNEL (in bytes) on the board
Type 0 for 2GB; 1 for 1GB; 2 for 512MB; 3 for 256MB; 4 for 128MB; 5 for 64MB; 6 for 32MB
Note, if there are two chip selects per channel, then input the combined density of
both chip selects per channel

>>> System freezes here after this!

[igorpadykov]

Hi James

may be useful to check memory configurations for Warp7 (MX7S&LPDDR3) board

u-boot-fslc/imximage.cfg at 2018.09+fslc · Freescale/u-boot-fslc · GitHub 

WaRP7 · GitHub 

For ddr test try to change signals drive strength for i.MX7S and memory (mode register MR3[DS]).

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[jjamesson]

Hi, Igor,

Thanks for the reply. I have tested the Warp 7 DDR setup as you suggested, resulting with the same errors. Regarding the signal strength, I tried changing the following registers for the IMX7S chip in the MX7D_DDR3_register_programming_aid_v09.ds file under the scripts folder:

0x3079009C (DDR_PHY_DRVDS_CON0)   --> Tried higher impedance values for all signals

0x307900C0 (DDR_PHY_ZQ_CON0)          --> Tried higher impedance values for [ZQ_MODE_DDS],

also without any improvements. I'm not sure how to change the registers for the LPDDR3 from the .ds/.inc file, though. Any suggestions on how I do this or continue with this problem?

With regards,

James

[igorpadykov]

Hi James

if these hints did not help suggest to proceed with help of

Commercial Support and Engineering Services | NXP 

Best regards
igor