Conditions of PL310 internal access request

[ko-hey]

Hi all

I'm using i.MX6Solo and have a question about ERR005198.

I can't understand the conditions of PL310 internal access request.

According to the errata, there are following description.

I understand the information will be sampled when PL310 requested.

This information is associated with each individual RAM access, and is only meant to be sampled

by the PL310 internal access requestor at precise cycles, depending on the programmable latencies

of the accessed RAM.

What situation will make the PL310 internal access request ?

Ko-hey

[art · Accepted solution]

There is so-called Internal instruction and data prefetch engine within the L2 cache controller that periodically generates internal accesses to the L2 cache RAM. For more information, please refer to the corresponding ARM document:

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0246h/DDI0246H_l2c310_r3p3_trm.pdf

Have a great day,
Artur

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[ko-hey]

Hi Artur

Thank you for reply.

Do you mean that there are no particular conditions that PL310 internal access are requested ?

ko-hey

[art]

The details of the internal prefetch engine operation are described in the document I' ve pointed to you laast time.

Best Regards,

Artur