About protection circuit for the USB VBUS/BP/BM signals to protect the latch-up in i.MX6DQ.

[keitanagashima]

Dear Sir or Madam,

Hello.

My customer assume the case of connecting the USB OTG device with no input the power to i.MX6.

Until a power is supplied to MX6 from PMIC, is it necessary to design a protection circuit to the i.MX6DQ's USB VBUS/BP/BM signals, to protect the latch-up occurrence?

(BTW, the protection circuit isn't implemented on FSL's SABRE board)

Best Regards,

Keita

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[art]

The USB OTG protection circuit is implemented on the i.MX6 SABRE SD board. Please refer to the schematic SPF-27392 Rev.C3, Sheet 11. These are the following protection components: U12, TVS1, Q512 to Q515 with surrounding circuits.

Have a great day,
Artur

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[robertferanec]

Artur, Yuri,

I am now confused. See 4.2.1 Power-Up Sequence note in i.MX 6Dual/6Quad Applications Processors for Industrial Products http://cache.freescale.com/files/32bit/doc/data_sheet/IMX6DQIEC.pdf​ page 31:

USB_OTG_VBUS and USB_H1_VBUS are not part of the power supply sequence and can be powered at any time.

Note: Maybe, you were referring to Errata: ERR006281 USB: Incorrect DP/DN state when only VBUS is applied http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf but it says nothing about locking up or damaging the CPU ... it just may cause a problem if charger feature is used, which is logical.

From the datasheet note I understand, that VBUS can be connected anytime (even in case no other voltage is connected) and it will not affect booting process (e.g. locking up CPU) or damage CPU. Am I wrong or this is a mistake in datasheet?

Thank you very much for your confirmation.

- Robert

[Yuri]

Hello,

"USB_OTG_VBUS and USB_H1_VBUS are not part of the power supply sequence

and can be powered at any time" - assuming  VDD_VSNVS_IN is always (or, at least, first)

applied.

Regards,

Yuri. 

[keitanagashima]

Hi Artur,

Thank you for your reply.

I have an additional question.

Refer to schematic again.

I couldn't find the protection circuit for USB_OTG_DN / USB_OTG_DP.

If i.MX6 has no power, is it possible to input the power into i.MX6's D+/D-?

Best Regards,

Keita

[Yuri]

Also, from the AI design :

USB_OTG_ID could cause backfeed through ESD Protection scheme, when

P3V3_DELAYED is not powered up. Therefore, pin 5 of the SRV05-4 is not

connected to a postive supply.

[keitanagashima]

Hi Yuri,

Sorry for my delay reply.

I have additional question.

My understanding is below.

When i.MX6 is not powered with connecting the PC and i.MX6 board, USB VBUS power = 0V protected by U12, TVS1, Q512, Q515 on i.MX6Q SABRE-AI.

But, I consider that "USB_OTG_DN" and "USB_OTG_DP" lines supplied the some voltage.

So, we worried about the latch-up by the voltage be applied from the USB differential-signal.

Is the protection circuit necessary for USB differential-signal line?

or

Are i.MX6's "USB_OTG_DN" and "USB_OTG_DP" pin state Hi-Z during power off?

Best Regards,

Keita

[Yuri]

  Note, in order to protect the i.MX6 processor, the USB 5V (VBUS) should not be applied to
the i.MX6 (VBUS pins), if VDD_VSNVS_IN is not powered on, because the LDO_USB internal

regulator requires VSNVS provided to work correctly.

Regards,

Yuri.

[Yuri]

The scheme, shown above is enough for USB D+ / D- signals protection.

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[keitanagashima]

Hi All,

Do you have any update?

Best Regards,

Keita