About TDSR time in Figure 13-14

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About TDSR time in Figure 13-14

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goto11
Contributor III

Hello,community

About TDSR time in Figure 13-14 of i.MX 7Dual Applications Processor Reference Manual
The low time of the RD signal on the LCD side is min355ns.
Is the TDSR time the same as DISPLAY CLOCK (pix_clk)?
What equation should be used to calculate the value of which register to set TDSR to 2.8MHz (1 / 355ns)?

Best Regards,
Goto

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Yuri
NXP Employee
NXP Employee

 

Hello,

 

 

  The timing parameters TCS, TCH, TDSR and TDHR are programmable. Use LCD Interface

Timing Register (LCDIFx_TIMING) and “Code Example to Initialize the eLCDIF in MPU Write Mode”

chapter in the RM. The timing values are set as number of DISPLAY CLOCK (pix_clk) cycles.

 

Have a great day,

Yuri

 

 

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633件の閲覧回数
Yuri
NXP Employee
NXP Employee

 

Hello,

 

 

  The timing parameters TCS, TCH, TDSR and TDHR are programmable. Use LCD Interface

Timing Register (LCDIFx_TIMING) and “Code Example to Initialize the eLCDIF in MPU Write Mode”

chapter in the RM. The timing values are set as number of DISPLAY CLOCK (pix_clk) cycles.

 

Have a great day,

Yuri

 

 

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Note:

- If this post answers your question, please click the "Mark Correct" button. Thank you!

- We are following threads for 7 weeks after the last post, later replies are ignored

 

Please open a new thread and refer to the closed one, if you have a related question at a later point in time.

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