Hello,Community
As shown below, at power down, CLK, CMD and DATA must be logic 0.
For example, if you use SW_MUX_CTL_Register(IOMUXC_SW_MUX_CTL_PAD_SD1_CLK) for ALT0_SD1_CLK and use it as a clock, do you have to perform the following processing at power down?
Or can the program force a logical 0 to be output?
1.Change the allocation to 100kPD(IOMUXC_SW_PAD_CTL_PAD_SD1_CLK).
2. Change the allocation to ALT5_GPIO5_IO3(IOMUXC_SW_MUX_CTL_PAD_SD1_CLK).
3. Assign to input with GPIOx_GDIR.
best regards
Goto
Solved! Go to Solution.
Hi GoTo
you are right, one can force signals to logical 0 in software
using your sequence.
Best regards
igor
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Hi GoTo
you are right, one can force signals to logical 0 in software
using your sequence.
Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
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