m4 primary part dual core

[karina_valencia]

From  xuewei.liu@honeywell.com

Dear support,

we have a M4 QSPIprimary part, PVF62GN151CMK40. but we want to use the A5 core to run MQX,then the M4 stay in idle state.  What the code would be?

Questions2, How to set the QSPI XIP project to generate the load image for the M4 primary part .

Thanks&Regards

(SR related 1-1065677828)

[juangutierrez]

Hi

I think your M4 code, should just kick off the A5 by setting the entry_point of the A5 code just before waking it up.

    /* Set entry function for secondary core. */

    SRC->GPR[2] = a5_entry_point_address;

    /* Wakes up the secondary (non-master) core. */

    CCM->CCOWR = 0x15a5a;

    /* Keep Primary core waiting for interrupt (WFI) */

    __asm(" wfi");

This is the same way it is used when A5 is the primary code. I think it should also applied when M4 is the primary.

Regarding Question number2

In DS5 you can generate a project for the A5 code and generate a c array output from the elf output by

setting a Post-build step like this

fromelf --cadcombined a5Project.axf --output a5ProjectImage.c

Then you can use another quadspi loader project that initializes, erase and configure the QuadSPI on writing mode.

(Please refer to the quadspi-load project in the set of examples released)

This project will place in DDR or SRAM the object file for the a5ProjectImage then at runtime you can copy the contents to the QuadSPI. You only need to add the a5ProjectImage.c and modify the DDR_QuadSPI_Load scatter file to add the name of the corresponding object file.

; External applicatin is at this location and used to program QuadSPI memory

EXTERNAL_APPLICATION 0x80080000

{

  EXTERNAL_CODE +0

  {

      a5ProjectImage.o(+RW)

  }

   EXTERNAL_CODE_END ImageLImit(EXTERNAL_CODE) EMPTY 0 {}

}

Be aware that you need to --keep=a5ProjectImage.o to the linker options

[xueweiliu]

Hi, Juan Antonio Gutierrez Rosas

We have M4 Primary part, but we want to evaluate VF5XX part in deed. So all my question is about how to let the chip work as an A5 Primary part.

1. The kick off code should execute before all the code start or place after M4 core initializes the stack, vector table and PLL like the dualcore demo? And I am confused about that which core should do the initialization work, including initialize the stack, vector table and clock?

2. Could you give an example for how to set the image project in IAR?

Thanks!

[juangutierrez]

You can place the kick off code at the entry point, or in main function. As long as the you keep the ivt (image vector table) code that ROM needs to ensure you reach the entry point. I think you can do the rest of the initialization in the M4 code.

You can check the example project GettingStarted.ewp at your local installation ( i.e. C:\Program Files\IAR Systems\Embedded Workbench 6.5\arm\examples\Freescale\VF6xx\TWR-VF600\build\iar\projects\getting_started).

Im using  IAR Embedded Workbench for ARM 6.50.5.4862

For QSPI XIP in debugger options setup macros they are using the

$PROJ_DIR$\..\..\..\..\build\iar\config\init_QSPI.mac

Also they are overriding the default board file with

$TOOLKIT_DIR$\config\flashloader\Freescale\FlashTWR600A5_QSPI.board

These scripts will allow you to flash the QaudSPI.

I also will try to get an M4 primary board and try to make an example as soon as I have some bandwith

[xueweiliu]

Hi Juan, do you have any updates on this? We are in trouble with this, we can download the code to QSPI flash but can not boot from it.

Thanks！

[anthony_huereca · Accepted solution]

Make sure the address you put in the boot header is the starting address of the M4 code plus 1. So if the first instruction is at 0x2000_0400, put in the boot header the value of 0x2000_0401

This is because the M4 is expecting an odd address since it operates in thumb mode. This helped another customer previously as that was the key they were missing.

[juangutierrez]

Hi,

Sorry I have not had enough time me lately.

Do you have any idea if reaching the code that enables the A5 or are you getting stuck in the ROM code?

If you can connect with JTAG/lauterbach maybe you can place a breakpoint at your entry point and see if you are reaching that code or the error happens before.

Also make sure you are modifying the ivt structure in your .ivt section to point entry to the start function you have the code that enables the A5

struct _ivt_ {

    /** @ref hdr with tag #HAB_TAG_IVT, length and HAB version fields

     *  (see @ref data)

     */

    uint32_t hdr;

    /** Absolute address of the first instruction to execute from the

     *  image

     */

    uint32_t entry;

    /** Reserved in this version of HAB: should be NULL. */

    uint32_t reserved1;

    /** Absolute address of the image DCD: may be NULL. */

    uint32_t dcd;

    /** Absolute address of the Boot Data: may be NULL, but not interpreted

     *  any further by HAB

     */

    uint32_t boot_data;

    /** Absolute address of the IVT.*/

    uint32_t self;

    /** Absolute address of the image CSF.*/

    uint32_t csf;

    /** Reserved in this version of HAB: should be zero. */

    uint32_t reserved2;

} ivt;