Vybrid Ballast Transistor + AN4807 Clarification

[GordyCarlson]

This inquiry directed to @Jiri Kotzian regarding AN4807 - Vybrid Power app note which he authored.

We are using an external switcher to supply the core power per the guidance of section 8.5 of the app note. The only difference is the BJT is being supplied from 1.8V instead of 1.5V in the app note. I  I believe the circuit in section 8.5 of the app note does not work in all cases, specifically when the 1.2V switcher voltage is less than what the internal LDO thinks the core voltage should be.

My questions specifically are:

1.   Has Freescale or one of their customers successfully implemented the circuit shown in section 8.5 of the app note?
2.   If so have they tested the case where the switcher supply is less than the internal LDO regulated voltage?

    3.   If yes is there something we are missing or have done incorrectly in our design or something we need to do internally in the processor to make this work (e.g. disable the BCTL signal)?  Besides the power issue I believe this may result in long-term damage (and a shortened life) of the part as I believe the current implementation is sourcing (significantly) more than the rated current out the BCTL signal.

  Attached is the schematic of that part of the circuit.  Other notes about our circuit and our observations below.

V1P2_GPP is connected directly to the GPP’s ( General Purpose Processor) core power input.

V1P2 is a switching power supply.

V1P2_SW_PWR_EN and V1P2_LDO_PWR_EN are connected to (3.3V) GPIOs on the Vybrid.

V1P2_BCTRL is connected to the Vybrid’s BCTL pin.

Our switcher output voltage is slightly lower than what the processor regulates to when using the LDO with the external BJT. When we move over to the switcher the BCTRL signal still seems to be trying to regulate the core supply. Because the switcher voltage is below what the LDO thinks it should be it drives (or tries to drive) the BCTRL signal to the rail (which seems to be 3.3V). This then seems to be backfed through the BJT to the 1.8V rail.

With the part installed I measure 1.8V at the collector, 1.8V at the emitter and ~2.6V at the base.

When I remove the part (after the processor has booted and moved to the switcher) I measure 1.8V at the collector, <100mV at the emitter, and ~3.2V at the base.

When I remove the part I see the 3.3V supply power drop by ~100mW, 1.8V power supply increase by ~30mW, and the overall power drop by ~50mW (so ~20mW is going somewhere else, I suspect the core rail itself).

This seems to be a fundamental issue with the design presented in the app note. (which I believe is implemented as presented in our design).

[ericaverill]

The datasheet states that the 3.3V supply (VDD33) should be up before the 1.2V supply (VDD). Given that the 1.2V supply is generated by the processor isn't this always the case? Does the sequencing apply to the supply which is connected to the collector of the ballast transistor (1.8V in our case)?

[jiri-b36968]

Hi Eric,

After power up (3.3V power rail) Vybrid SoC tests it and if it is correct, HPREG is enabled, boot continues …

If this power rail is used for powering ballast transistor then you are safe - this is how Vybrid power system is designed - one main power rail (not count USB and DDR voltage rails).

But as mentioned in above discussion, when you use different power supply for powering ballast transistor to save a power, then you have to ensure that this power supply is ready prior to 3.3V power rail. The best way is hardwired solution, for example to use 1.5/1.8V power supply's output as a enable signal for 3.3V power supply - done on TWR-VF65.

/Jiri

[ericaverill]

Hi we are continuing to implement and review this circuit and had one more concern arise:

If you are powered off the external switcher with a voltage below the LDO's regulated voltage the Vybrid will drive the BCTRL signal to it's rail in an attempt to regulate it (as was described above). If the processor switches back to the LDO is there a fear of a spike on the core voltage due to the BCTRL signal not being able to react fast enough to the rising input voltage?

[jiri-b36968]

Hi Eric,

yes this is relevant fear. As mentioned before, right timing is required. BCTL loop has given response time. So you need to synchronize with it. All "spikes" have to be within VDD core voltage 1.16 - 1.26 V.

/Jiri

[ericaverill]

Jiri,

Does the example schematic provided earlier in this thread address this potential issue? If so how?

[jiri-b36968]

Hi Eric,

yes it is prepared for it, but I'm not sure how far it is tested. Schematic I sent for just for illustration. Important is timing. Timing constant can be set in the code or in HW and by value of capacitors (generally RC constant of FETs resistance and capacitance of capacitors). It have to be simply tuned. You have to decide if you want to use one control signal from Vybrid and more complicated HW or two control signals and less complicated HW - constants could be tuned in SW.

I recommend one HW signal for safety reasons.

/Jiri

[ericaverill]

So it is the make-before-break timing which prevents the surge (basically allowing the other supply to absorb the surge from the LDO)?

[jiri-b36968]

Hi Eric,

Right. You need to be sure that power is always available and also ensure that both supply not supplying continuously.

/Jiri

[naoumgitnik]

Dear Gordon,

Although you formally addressed your question to  jiri-b36968 (who, I guess, has already successfully supported you in the past), I decided to jump in since we both closely worked on the scheme of interest. The other reason is that Jiri and myself are in different time zones (about 1/3 of a day apart, and I am currently in the office) + I will be out of the office tomorrow, so, it would expedite the issue resolution if we both participated in it.

Please, find my answers below:

• Attached is a excerpt from the Vybrid Hardware Development Guide explaining the structure of the internal 1.2V regulator. The document will be published soon; at the same time, I'd strongly recommend you to request its draft from your local Freescale FAE. (You may look here as well -  in https://community.freescale.com/message/331829).
• The 1.2V switcher's voltage shall be within the min-max limits provided in the Vybrid datasheet.
• Freescale tested this "switching scheme" with manually switching the core between the linear and switcher regulators (with overlapping them in time <- important!), and a few customers implemented it using their software. When Vybrid is already running from the 1.2V switcher, the BCTRL pin is "out of the game" and its level does not matter.

BTW, what is the reason for having 240 Ohms to GND on the BCTRL pin, please? - There is no such resistor in our documentation.

Sincerely, Naoum Gitnik.

[GordyCarlson]

Thanks for your advice Naoum, very helpful.  we addressed it to Jiri as he is the author of the app note, but your comments are VERY welcome also.  We have removed the 240 ohm resistor,  the customer engineer also later realized he didn't need it.  Will review the draft copy of the document you provided. I'm sure there will be other helpful items in there as well.  Thanks!

[naoumgitnik · Accepted solution]

Hello Gordon,

Presented below is the second FET circuitry from the schematic provided by Jiri. It controls the NPN transistor's connection.

Just to explain this schematic a bit:

- Ignore the switcher's output option of 1.8V as irrelevant for your use case.

- The RC values providing required timing for on/off/overlapping are preliminary and might need tuning.

- Transistors with only 2 pins connected are used as diodes; the only purpose of that was to simplify the board BOM.

In addition to what Jiri already mentioned, using glue logic lowers number of Vybrid's IOs used for the circuit control, which might be important in your use case.

[jiri-b36968, thanks a lot!]

Sincerely, Naoum Gitnik.

[GordyCarlson]

Thank you both Naoum and Jiri!  Your answers have both been very helpful.  Customer is evaluating these approaches and guidance.  Will advise if we need anything more.

best,

Gordy

[ericaverill]

Thanks, the additional detail on these schematics helps.

One difference between out schematic and yours is the direction of the FET in line with the LDO (Q8 in your schematic above and Q10 in our schematic). If we reverse the FET it will prevent the LDO backfeeding onto the 1.2V processor supply.

What we also found however that BCTRL was being driven through the BJT back onto it's supply (1.2 or VDDREG_CAP in your schematic above) when the processor's LDO control thinks the input voltage is too low and the switcher was selected. It seems like this would be an issue with your circuit above, do you agree? We placed a diode in series with the BJT's collector and that seemed to fix things. That way even if BCTRL is being driven to the rail there are diodes blocking the path on both the emitter and collector.

[naoumgitnik]

Dear ericaverill,

Please, take a look at the Re: Power supply for Vybrid core thread, specifically my reply dated 'May 30, 2013 4:15 PM', which details the source-switching sequencing. The schematic Jiri and myself provided earlier is based on it.

The major principle of this approach is that "Vybrid powers up / down and switches between Power Modes same way as before", i.e. when it only uses the linear regulator!

Regarding your "If we reverse the FET, it will prevent the LDO back-feeding onto the 1.2V processor supply." statement. - The FET diodes' directions are to meet this requirement. E.g., when the linear regulator is running but the switch-mode one is not yet, the reverse-biased diode isolates the core power rail from the still unchanged switch-mode regulator's output capacitor (otherwise it would be charging from the core rail).

This requirement, to isolate 2 regulators from each other as much as possible, except for short period of time of their overlapping, is important for the switch-mode regulator as well - e.g., it is designed to be turned on with the output capacitor discharged.

Based on my support experience, some customers trying to "cut corners" to simplify the scheme have been experiencing issues with Vybrid and/or the switch-mode voltage regulator.

I am having difficulties understanding your "BCTRL was being driven through the BJT back onto it's supply... We placed a diode in series with the BJT's collector and that seemed to fix things" phrase, used diodes, etc. If it is still applicable, may you provide more details, please, like illustrations, etc.?

[Please, also take a look at the newly published http://cache.freescale.com/files/microcontrollers/doc/user_guide/VYBRIDHDUG.pdf.]

Sincerely, Naoum Gitnik.

[GordyCarlson]

[ericaverill]

Naoum,

Regarding your last point about my comment on the BCTRL signal I'll use your circuit as an example.

Assume that the LDO is regulated by the processor to 1.2V but the switcher puts out a slightly lower voltage. When the processor is transitioned over to the switcher the LDO control will still be trying to regulate the core voltage via the BCTRL signal. Because the input voltage is lower than it expects it will drive the BCTRL signal higher in an effort to raise the core voltage (which will not work because it's no longer actually controlling core voltage, the switcher is). The FET (Q8 in the schematic above) is open so no current will be able to flow out the emitter of the BJT. The collector is at VDDREG_CAP in your circuit (or whatever J179 is jumpered to), on our board it's 1.8V. It appears that BCTRL can be driven to 3.3V. This puts the base of the BJT at ~3.3V and the collector at 1.8V, forward biasing the b-c junction and current flows from the base to the collector, effectively backfeeding the supply with as much current as BCTRL is capable of suppling.

Does this make sense?

[naoumgitnik]

Dear Eric,

Thaks for your explanation - now I see what you mean.

We do not have such an issue in our design - the collector is at 3.3V, i.e. always at higher voltage than the BCTRL pin.

If having 1.8V on the collector is mandatory in your design, you will indeed need a diode in series with the collector (better of a Schottky type - to lower voltage drop).

Regards, Naoum Gitnik.

[ericaverill]

Thanks Naoum, so you would agree that the solution for this fix is to either use 3.3V as the supply to the BJT or to add a diode in series with the collector of the BJT?

[naoumgitnik]

Yes.

[naoumgitnik]

Dear Gordon,

We have also recommended using SI2312BDS as a power switch but have no feedback as of how well it operated.

It is easy to be controlled with logic levels (0 / 3.3V) directly from the processor + its thresholds look more or less meeting the R[ds-on] requirements.

Regards, Naoum Gitnik.

[jiri-b36968]

Hi Gordon,

thank you Naoum. Figure 6 in AN is illustrative. The option from 8.5 was implemented, but schematic was more complicated.

I personally prefer to use option from 8.4. Because if you implement correct power enable like in TWR-Vf65 rev.H (3V3 after 1V5 to ensure that 1.5V is present, 3V3 is checked by Vybrid) then all is hardware based a safe.

The option from 8.5 chapter requires correct timing between switching power supplies especially when low power modes are used. Not saying to not use it, but it would need more careful design. For example: I would prefer to have just one pin to switch power supply since SW can hang just between disabling one FET and enabling second FET. And yes I see potential problem in your schematic. LDO will try to increase output voltage using BCTRL pin up to 2.6V (depending on your external 1.2V power supply voltage) so on Q12 base we can have 2V and through reverse diode in Q10 it will flow to V1P2. Which will probable tend to decrease BCTRL voltage but it can overload BCTRL pin (max 20mA) Schematic have to be improved or use option from 8.4

Just for illustration

/Jiri